NE5532PSE4 参数 Datasheet PDF下载

SLLS693F – MAY 2007 – REVISED JANUARY 2010

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4.3

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4.2.63 GPIO C Control Register

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4.2.64 GPIO D Control Register

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4.2.65 GPIO Data Register

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4.2.66 TI Proprietary Register

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4.2.67 TI Proprietary Register

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4.2.68 TI Proprietary Register

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4.2.69 TI Proprietary Register

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4.2.70 TI Proprietary Register

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4.2.71 TI Proprietary Register

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4.2.72 Subsystem Access Register

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4.2.73 General Control Register

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4.2.74 Downstream Ports Link PM Latency Register

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4.2.75 Global Switch Control Register

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4.2.76 Advanced Error Reporting Capability ID Register

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4.2.77 Next Capability Offset/Capability Version Register

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4.2.78 Uncorrectable Error Status Register

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4.2.79 Uncorrectable Error Mask Register

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4.2.80 Uncorrectable Error Severity Register

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4.2.81 Correctable Error Status Register

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4.2.82 Correctable Error Mask Register

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4.2.83 Advanced Error Capabilities and Control Register

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4.2.84 Header Log Register

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PCI Express Downstream Port Registers

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4.3.1

PCI Configuration Space (Downstream Port) Register Map

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4.3.2

Vendor ID Register

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4.3.3

Device ID Register

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4.3.4

Command Register

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4.3.5

Status Register

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4.3.6

Class Code and Revision ID Register

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4.3.7

Cache Line Size Register

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4.3.8

Primary Latency Timer Register

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4.3.9

Header Type Register

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4.3.10 BIST Register

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4.3.11 Primary Bus Number

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4.3.12 Secondary Bus Number

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4.3.13 Subordinate Bus Number

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4.3.14 Secondary Latency Timer Register

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4.3.15 I/O Base Register

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4.3.16 I/O Limit Register

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4.3.17 Secondary Status Register

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4.3.18 Memory Base Register

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4.3.19 Memory Limit Register

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4.3.20 Pre-fetchable Memory Base Register

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4.3.21 Pre-fetchable Memory Limit Register

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4.2.62

GPIO B Control Register

4

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