XIO3130
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BIT
SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-42. Bit Descriptions – Downstream Ports Link PM Latency Register (continued)
FIELD NAME
ACCESS
DESCRIPTION
L1 exit latency. This field is used to program the maximum latency for the PHY to exit the
L1 state. This is used to set the L1 Exit Latency field in the Link Capabilities register.
000 – Less than 1 ms
001 – 1 ms up to less than 2 ms
010 – 2 ms up to less than 4 ms
011 – 4 ms up to less than 8 ms
100 – 8 ms up to less than 16 ms (default)
101 – 16 ms up to less than 32 ms
110 – 32 ms to 64 ms
2:0
L1_EXIT_LAT
rw
111 – More than 64 ms
4.2.75 Global Switch Control Register
This read/write register is used to control various functions across the entire XIO3130.
PCI register offset:
Register type:
EAh
Read/Write; Read Only; Clear by a Write of One; Sticky
0004h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-43. Bit Descriptions – Global Switch Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
Downstream ports L0s independence
15:7
RSVD
r
0 – Downstream ports (all) Tx L0s entry dependent on whether upstream Rx is in L0s according to
6
DP_L0S_IND
rw
PCI Express Base Specification, section 5.4.1.1.1.
1 – Downstream ports Tx L0s entry not dependent on whether upstream Rx is in L0s.
Reserved. When read, this bit returns zero.
5
4
3
RSVD
DEFER_L_EXIT
RSVD
r
rw
r
Defer L0s, L1 exit. This bit configures logic to not automatically power up all downstream ports when
the upstream port receives a downstream flowing packet.
This field is loaded from EEPROM (when present) and reset with PERST.
Reserved. When read, this bit returns zero.
D1 support. This bit enables whether all PCI Express XIO3130 functions are capable of D1 support.
The field controls (1) the D1_SUPPORT bit in the Power Management Capabilities register for all
XIO3130 ports, and (2) bit 1 in the 5-bit PME_SUPPORT field in the Power Management Capabilities
register for all XIO3130 ports.
2
1
D1_SUPPORT
rw
rw
0 – D1 not supported
1 – D1 supported
This field is loaded from EEPROM (when present) and reset with PERST.
PCI Hot Plug PME message enable. This bit enables PME_Turn_Off/PME_TO_Ack messages when
power is shut off to a slot using the PC_CTL bit in the Slot Control register for downstream ports.
HP_PME_MSG
_EN
0 – Disable PME_Turn_Off / PME_TO_Ack messages for slot power control
1 – Enable PME_Turn_Off / PME_TO_Ack messages for slot power control
This field is loaded from EEPROM (when present) and reset with PERST.
Copyright © 2007–2010, Texas Instruments Incorporated
XIO3130 Configuration Register Space
79
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