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NE5532PSE4 参数 Datasheet PDF下载

NE5532PSE4图片预览
型号: NE5532PSE4
PDF下载: 下载PDF文件 查看货源
内容描述: [DUAL OP-AMP, 5000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, PLASTIC, SO-8]
分类和应用: 放大器光电二极管
文件页数/大小: 142 页 / 1062 K
品牌: TI [ TEXAS INSTRUMENTS ]
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XIO3130  
SLLS693FMAY 2007REVISED JANUARY 2010  
www.ti.com  
4.2.74 Downstream Ports Link PM Latency Register  
This read/write register is used to program L0s and L1 exit latencies for all XIO3130 downstream ports.  
Similar information is provided in a separate register for the upstream port.  
PCI register offset:  
Register type:  
E8h  
Read/Write; Read Only  
3F24h  
Default value:  
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-42. Bit Descriptions – Downstream Ports Link PM Latency Register  
BIT  
FIELD NAME  
ACCESS  
DESCRIPTION  
Reserved. When read, these bits return zeros.  
Endpoint L0s acceptable latency. This field is used to program the maximum acceptable  
15:14  
RSVD  
r
latency when exiting the L0s state. This field is used to set the L0s Acceptable Latency field  
in the Device Capabilities register.  
000 – Less than 64 ns  
001 – 64 ns up to less than 128 ns  
010 – 128 ns up to less than 256 ns  
011 – 256 ns up to less than 512 ns  
100 – 512 ns up to less than 1 ms  
101 – 1 ms up to less than 2 ms  
13:11  
EP_L0S_LAT  
rw  
110 – 2 ms to 4 ms  
111 – More than 4 ms (default)  
This field is loaded from EEPROM (when present) and reset with PERST.  
Endpoint L1 acceptable latency. This field is used to program the maximum acceptable  
latency when exiting the L1 state. This field is used to set the L1 Acceptable Latency field in  
the Device Capabilities register.  
000 – Less than 1 ms  
001 – 1 ms up to less than 2 ms  
010 – 2 ms up to less than 4 ms  
10:8  
EP_L1_LAT  
rw  
011 – 4 ms up to less than 8 ms  
100 – 8 ms up to less than 16 ms  
101 – 16 ms up to less than 32 ms  
110 – 32 ms to 64 ms  
111 – More than 64 ms (default)  
This field is loaded from EEPROM (when present) and reset with PERST.  
Reserved. When read, these bits return zeros.  
7:6  
5:3  
RSVD  
r
L0s exit latency. This field is used to program the maximum latency for the PHY to exit the  
L0s state. This is used to set the L0s Exit Latency field in the Link Capabilities register.  
000 – Less than 64 ns  
001 – 64 ns up to less than 128 ns  
010 – 128 ns up to less than 256 ns  
011 – 256 ns up to less than 512 ns  
100 – 512 ns up to less than 1 ms (default)  
101 – 1 ms up to less than 2 ms  
110 – 2 ms to 4 ms  
L0S_EXIT_LAT  
rw  
111 – More than 4 ms  
78  
XIO3130 Configuration Register Space  
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Product Folder Link(s): XIO3130