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NE5532PSE4 参数 Datasheet PDF下载

NE5532PSE4图片预览
型号: NE5532PSE4
PDF下载: 下载PDF文件 查看货源
内容描述: [DUAL OP-AMP, 5000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, PLASTIC, SO-8]
分类和应用: 放大器光电二极管
文件页数/大小: 142 页 / 1062 K
品牌: TI [ TEXAS INSTRUMENTS ]
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XIO3130  
www.ti.com  
SLLS693FMAY 2007REVISED JANUARY 2010  
Table 4-48. Correctable Error Mask Register (continued)  
BIT  
FIELD NAME  
ACCESS  
DESCRIPTION  
REPLAY_NUM rollover mask.  
0 – Error condition is unmasked  
1 – Error condition is masked  
Bad DLLP error mask.  
8
REPLAY_ROLL_MASK  
rwh  
7
BAD_DLLP_MASK  
rwh  
0 – Error condition is unmasked  
1 – Error condition is masked  
Bad TLP error mask.  
6
5:1  
0
BAD_TLP_MASK  
RSVD  
rwh  
r
0 – Error condition is unmasked  
1 – Error condition is masked  
Reserved. Return zeros when read.  
Receiver error mask.  
RX_ERROR_MASK  
rwh  
0 – Error condition is unmasked  
1 – Error condition is masked  
4.2.83 Advanced Error Capabilities and Control Register  
The Advanced Error Capabilities and Control register allows the system to monitor and control the  
advanced error reporting capabilities.  
PCI register offset:  
Register type:  
118h  
Read Only, Read/Write  
0000 00A0h  
Default value:  
BIT NUMBER  
RESET STATE  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
Table 4-49. Advanced Error Capabilities and Control Register  
BIT  
FIELD NAME  
ACCESS  
DESCRIPTION  
Reserved. Return zeros when read.  
31:9  
RSVD  
r
Extended CRC check enable.  
8
7
6
ECRC_CHK_EN  
ECRC_CHK_CAPABLE  
ECRC_GEN_EN  
rwh  
r
0 – Extended CRC checking is disabled  
1 – Extended CRC checking is enabled  
Extended CRC check capable. This read-only bit returns a value of ‘1’ indicating that  
the bridge is capable of checking extended CRC information.  
Extended CRC generation enable.  
rwh  
0 – Extended CRC generation is disabled  
1 – Extended CRC generation is enabled  
Extended CRC generation capable. This read-only bit returns a value of ‘1’  
indicating that the bridge is capable of generating extended CRC information.  
5
ECRC_GEN_CAPABLE  
FIRST_ERR  
r
First error pointer. This five-bit value reflects the bit position within the Uncorrectable  
Error Status register corresponding to the class of the first error condition that was  
detected.  
4:0  
rh  
Copyright © 2007–2010, Texas Instruments Incorporated  
XIO3130 Configuration Register Space  
85  
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Product Folder Link(s): XIO3130