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NE5532PSE4 参数 Datasheet PDF下载

NE5532PSE4图片预览
型号: NE5532PSE4
PDF下载: 下载PDF文件 查看货源
内容描述: [DUAL OP-AMP, 5000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, PLASTIC, SO-8]
分类和应用: 放大器光电二极管
文件页数/大小: 142 页 / 1062 K
品牌: TI [ TEXAS INSTRUMENTS ]
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XIO3130  
www.ti.com  
SLLS693FMAY 2007REVISED JANUARY 2010  
4.3.7 Cache Line Size Register  
The Cache Line Size register is implemented by PCI Express devices as a read-write field for legacy  
compatibility, but has no impact on any PCI Express device functionality.  
PCI register offset:  
Register type:  
0Ch  
Read/Write  
00h  
Default value:  
BIT NUMBER  
RESET STATE  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.8 Primary Latency Timer Register  
This read-only register has no meaningful context for a PCI Express device, so it returns zeros when read.  
PCI register offset:  
Register type:  
0Dh  
Read only  
00h  
Default value:  
BIT NUMBER  
RESET STATE  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.9 Header Type Register  
This read-only register indicates that this function has a Type 1 PCI header. Bit seven of this register is  
zero, indicating that the XIO3130 downstream port PCI-to-PCI bridge is not a multifunction device.  
PCI register offset:  
Register type:  
0Eh  
Read only  
01h  
Default value:  
BIT NUMBER  
RESET STATE  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
4.3.10 BIST Register  
Since the XIO3130 does not support a built-in self test (BIST), this read-only register returns the value 00h  
when read.  
PCI register offset:  
Register type:  
0Fh  
Read only  
00h  
Default value:  
BIT NUMBER  
RESET STATE  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Copyright © 2007–2010, Texas Instruments Incorporated  
XIO3130 Configuration Register Space  
91  
Submit Documentation Feedback  
Product Folder Link(s): XIO3130