欢迎访问ic37.com |
会员登录 免费注册
发布采购

NE5532PSE4 参数 Datasheet PDF下载

NE5532PSE4图片预览
型号: NE5532PSE4
PDF下载: 下载PDF文件 查看货源
内容描述: [DUAL OP-AMP, 5000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, PLASTIC, SO-8]
分类和应用: 放大器光电二极管
文件页数/大小: 142 页 / 1062 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号NE5532PSE4的Datasheet PDF文件第76页浏览型号NE5532PSE4的Datasheet PDF文件第77页浏览型号NE5532PSE4的Datasheet PDF文件第78页浏览型号NE5532PSE4的Datasheet PDF文件第79页浏览型号NE5532PSE4的Datasheet PDF文件第81页浏览型号NE5532PSE4的Datasheet PDF文件第82页浏览型号NE5532PSE4的Datasheet PDF文件第83页浏览型号NE5532PSE4的Datasheet PDF文件第84页  
XIO3130  
SLLS693FMAY 2007REVISED JANUARY 2010  
www.ti.com  
Table 4-43. Bit Descriptions – Global Switch Control Register (continued)  
BIT  
FIELD NAME  
ACCESS  
DESCRIPTION  
Beacon detect disable. This bit disables beacon detection on all downstream ports and allows the  
reference macro to be placed in low power state during D3cold.  
0 – Beacon detection enabled  
0
BCN_DET_DIS  
rwh  
1 – Beacon detection disabled  
This field is loaded from EEPROM (when present) and reset with GRST.  
4.2.76 Advanced Error Reporting Capability ID Register  
This read-only register identifies the linked list item as the register for PCI Express Advanced Error  
Reporting Capabilities. The register returns 0001h when read.  
PCI register offset:  
Register type:  
100h  
Read only  
0001h  
Default value:  
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
4.2.77 Next Capability Offset/Capability Version Register  
This read-only register returns the value 0000h to indicate that this extended capability block represents  
the end of the linked list of extended capability structures. The least significant four bits identify the  
revision of the current capability block as 1h.  
PCI register offset:  
Register type:  
102h  
Read only  
0000h  
Default value:  
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4.2.78 Uncorrectable Error Status Register  
This register reports the status of individual errors as they occur. Software may clear these bits only by  
writing a 1 to the desired location.  
PCI register offset:  
Register type:  
104h  
Read Only, Cleared by a Write of one  
0000 0000h  
Default value:  
BIT NUMBER  
RESET STATE  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
80  
XIO3130 Configuration Register Space  
Copyright © 2007–2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): XIO3130