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NE5532PSE4 参数 Datasheet PDF下载

NE5532PSE4图片预览
型号: NE5532PSE4
PDF下载: 下载PDF文件 查看货源
内容描述: [DUAL OP-AMP, 5000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, PLASTIC, SO-8]
分类和应用: 放大器光电二极管
文件页数/大小: 142 页 / 1062 K
品牌: TI [ TEXAS INSTRUMENTS ]
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XIO3130  
www.ti.com  
SLLS693FMAY 2007REVISED JANUARY 2010  
4.2.72 Subsystem Access Register  
This register is a read/write register. The contents of this register are aliased to the Subsystem Vendor ID  
and Subsystem ID registers at PCI Offsets 84h and 86h for all PCI Express ports.  
PCI register offset:  
Register type:  
E0h  
Read/Write  
0000 0000h  
Default value:  
BIT NUMBER  
RESET STATE  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-40. Bit Descriptions – Subsystem Access Register  
BIT  
FIELD NAME  
ACCESS  
DESCRIPTION  
Subsystem ID. The value written to this field is aliased to the Subsystem ID register at PCI  
Offset 66h. This field is loaded from EEPROM (when present) and reset with PERST.  
31:16  
SubsystemID  
rw  
Subsystem Vendor ID. The value written to this field is aliased to the Subsystem Vendor  
ID register at PCI Offset 64h. This field is loaded from EEPROM (when present) and reset  
with PERST.  
15:0  
SubsystemVendorID  
rw  
4.2.73 General Control Register  
This register is a read/write register that is used to control various functions of the XIO3130.  
PCI register offset:  
Register type:  
E4h  
Read/Write; Read Only  
0000 0000h  
Default value:  
BIT NUMBER  
RESET STATE  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-41. Bit Descriptions – General Control Register  
BIT  
FIELD NAME  
ACCESS  
DESCRIPTION  
31:3  
RSVD  
r
Reserved. When read, these bits return zeros.  
2
1
0
TI_PROPRIETARY  
L1_DISABLE  
RSVD  
rw  
TI proprietary. This bit must not be changed from the specified default value.  
L1 disable. This bit may be used to disable software-directed L1 entry when in  
lower D-states (D1-D3). The value of L1_DISABLE is 0 (the default). Link  
power states are managed in accordance with the PCI Express base  
specification. When L1_DISABLE is 1, the upstream port of the XIO3130 does  
not enter L1 even when directed to do so through software.  
rw  
r
Reserved. When read, this bit returns zero.  
Copyright © 2007–2010, Texas Instruments Incorporated  
XIO3130 Configuration Register Space  
77  
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Product Folder Link(s): XIO3130