XIO3130
SLLS693F–MAY 2007–REVISED JANUARY 2010
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Table 4-36. Bit Descriptions – GPIO B Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
GPIO 6 Control. This field controls the GPIO6 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_BTN0
011 – Port 3 ACT_BTN2
100 – Port 1 PWRFLT0
101 – Port 3 PWRFLT2
110 – Port 1 MRLS_DET0
5:3
PCIE_GPIO6_CTL
rw
111 – Port 3 MRLS_DET2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If DPSTRP[1] == 1, this bit field is read only and reads back zero.
If the DN2_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO6 terminal
is directly mapped as the PWR_GOOD PCI Hot Plug terminal for port 3 and is no longer
available for use as a GPIO. In this situation these bits have no meaning and should be left
at their default value.
GPIO 5 Control. This field controls the GPIO5 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 EMIL_CTL0
011 – Port 3 EMIL_CTL2
100 – Port 1 ATN_LED0
101 – Port 3 ATN_LED2
110 – Port 1 PWR_LED0
2:0
PCIE_GPIO5_CTL
rw
111 – Port 3 PWR_LED2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If DPSTRP[1] == 1, this bit field is read only and reads back zero.
If the DN2_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO5 terminal
is directly mapped as the PWR_ON PCI Hot Plug terminal for port 3 and is no longer
available for use as a GPIO. In this situation these bits have no meaning and should be left
at their default value.
4.2.63 GPIO C Control Register
This register is used to control the function of the PCIE_GPIO 10 – 13 pins.
PCI register offset:
Register type:
C0h
Read/Write; Sticky
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
68
XIO3130 Configuration Register Space
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