XIO3130
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SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-44. Uncorrectable Error Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:21
RSVD
r
Reserved. Return zeros when read.
Unsupported Request error. This bit is asserted when an Unsupported Request error is
detected (i.e., when a request is received that results in the sending of a completion with
an Unsupported Request status).
20
UR_ERROR
rcuh
19
18
ECRC_ERROR
MAL_TLP
rcuh
rcuh
Extended CRC error. This bit is asserted when an Extended CRC error is detected.
Malformed TLP. This bit is asserted when a malformed TLP is detected.
Receiver overflow. This bit is asserted when the flow control logic detects that the
transmitting device has illegally exceeded the number of credits that were issued.
17
16
15
14
13
RX_OVERFLOW
UNXP_CPL
rcuh
rcuh
rcuh
rcuh
rcuh
Unexpected completion. This bit is asserted when a completion packet is received that
does not correspond to an issued request.
Completer abort. This bit is asserted when the completion to a pending request arrives with
Completer Abort status.
CPL_ABORT
CPL_TIMEOUT
FC_ERROR
Completion timeout. This bit is asserted when no completion has been received for an
issued request before the timeout period.
Flow control error. This bit is asserted when a flow control protocol error is detected either
during initialization or during normal operation.
Poisoned TLP. This bit is asserted when an outgoing packet (request or completion) has
been poisoned by setting the poison bit and has inverted the extended CRC attached to
the end of the packet.
12
PSN_TLP
rcuh
11:6
5
RSVD
SD_ERROR
DLL_ERROR
RSVD
r
rcuh
rcuh
r
Reserved. Return zeros when read.
Surprise down error. See Surprise Down ECN for a description of this error condition.
Data link protocol error. This bit is asserted if a data link layer protocol error is detected.
Reserved. Return zeros when read.
4
3:1
0
Undefined
r
The value read from this bit is undefined.
4.2.79 Uncorrectable Error Mask Register
The Uncorrectable Error Mask register controls the reporting of individual errors as they occur. When a bit
is set to one, the error status bits are still affected, but the error is not logged and no error reporting
message is sent upstream.
PCI register offset:
Register type:
108h
Read Only, Read/Write
0000 0000h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-45. Uncorrectable Error Mask Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Return zeros when read.
31:21
RSVD
r
Unsupported Request error mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
Extended CRC error mask.
20
UR_ERROR_MASK
rwh
rwh
19
ECRC_ERROR_MASK
0 - Error condition is unmasked.
1 - Error condition is masked.
Copyright © 2007–2010, Texas Instruments Incorporated
XIO3130 Configuration Register Space
81
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