XIO3130
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SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-46. Uncorrectable Error Severity Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Return zeros when read.
Unsupported Request error severity.
31:21
RSVD
r
20
19
18
17
16
15
14
13
UR_ERROR_SEVR
ECRC_ERROR_SEVR
MAL_TLP_SEVR
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Extended CRC error severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Malformed TLP severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Receiver Overflow severity.
RX_OVERFLOW_SEVR
UNXP_CPL_SEVR
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Unexpected Completion severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Completer Abort severity.
CPL_ABORT_SEVR
CPL_TIMEOUT_SEVR
FC_ERROR_SEVR
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Completion Timeout severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Flow Control error severity.
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Poisoned TLP severity.
12
11:6
5
PSN_TLP_SEVR
RSVD
rwh
r
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Reserved. Return zeros when read.
Surprise Down error severity.
SD_ERROR_SEVR
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Data Link Protocol error severity.
4
DLL_ERROR_SEVR
rwh
0 - Error condition is signaled using ERR_NONFATAL.
1 - Error condition is signaled using ERR_FATAL.
Reserved. Return zeros when read.
3:1
0
RSVD
r
r
Undefined
The value read from this bit is undefined.
4.2.81 Correctable Error Status Register
The Correctable Error Status register reports the status of individual errors as they occur. Software may
clear these bits only by writing a 1 to the desired location.
PCI register offset:
Register type:
110h
Read Only, Cleared by a Write of one
0000 0000h
Default value:
Copyright © 2007–2010, Texas Instruments Incorporated
XIO3130 Configuration Register Space
83
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