XIO3130
SLLS693F–MAY 2007–REVISED JANUARY 2010
www.ti.com
Table 4-53. Bit Descriptions – Status Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Received master abort. This bit is hardwired to zero. It is assumed that the relevant error
checking is unnecessary for the XIO3130 internal PCI bus.
13
MABORT
r
Received target abort. This bit is hardwired to zero. It is assumed that the relevant error
checking is unnecessary for the XIO3130 internal PCI bus.
12
TABORT_REC
r
Signaled target abort. This bit is hardwired to zero. It is assumed that the relevant error
checking is unnecessary for the XIO3130 internal PCI bus.
11
TABORT_SIG
PCI_SPEED
r
r
10:9
DEVSEL timing. These bits are read only zero because they do not apply to PCI Express.
Master data parity error. This bit is set when the downstream port receives a poisoned
completion or poisons a write request on the internal virtual PCI bus. This bit is never set if
the parity error response enable bit in the Command register is clear.
8
DATAPAR
rcu
Fast back-to-back capable. This bit does not have a meaningful context for a PCI Express
device and is hardwired to zero.
7
6
5
FBB_CAP
RSVD
r
r
r
Reserved. When read, this bit returns zero.
66-MHz capable. This bit does not have a meaningful context for a PCI Express device and is
hardwired to zero.
66MHZ
Capabilities list. This bit returns 1 when read, indicating that the XIO3130 supports additional
PCI capabilities.
4
CAPLIST
r
Interrupt status. This bit reflects the INTx interrupt status of the function. The XIO3130
forwards INTx messages from downstream ports to the upstream port.
3
INT_STATUS
RSVD
r
r
2:0
Reserved. When read, these bits return zeros.
4.3.6 Class Code and Revision ID Register
This read-only register categorizes the Base Class, Sub Class, and Programming Interface of the
XIO3130. The Base Class is 06h, which identifies the device as a bridge device. The Sub Class is 04h,
which identifies the function as a PCI-to-PCI bridge. The Programming Interface is 00h. In addition, the TI
chip revision is indicated in the lower byte (01h).
PCI register offset:
Register type:
08h
Read only
0604 0001h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Table 4-54. Bit Descriptions – Class Code and Revision ID Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Base class. This field returns 06h when read, which classifies the function as a bridge
device.
31:24
23:16
BASECLASS
r
Subclass. This field returns 04h when read, which specifically classifies the function as a
PCI-to-PCI bridge.
SUBCLASS
r
15:8
7:0
PGMIF
r
r
Programming interface. This field returns 00h when read.
Silicon revision. This field returns the silicon revision.
CHIPREV
90
XIO3130 Configuration Register Space
Copyright © 2007–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): XIO3130
TI [ TEXAS INSTRUMENTS ]
