XIO3130
SLLS693F–MAY 2007–REVISED JANUARY 2010
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Table 4-51. Extended Configuration Space (Downstream Port)
Register Name
PCI Express Advanced Error Reporting Capabilities ID
Offset
Next Capability Offset / Capability Version
100h
104h
Uncorrectable Error Status Register
Uncorrectable Error Mask Register
Uncorrectable Error Severity Register
Correctable Error Status Register
Correctable Error Mask
108h
10Ch
110h
114h
Advanced Error Capabilities and Control
Header Log Register
118h
11Ch
120h
Header Log Register
Header Log Register
124h
Header Log Register
128h
Reserved
12Ch-FFCh
4.3.2 Vendor ID Register
This 16-bit read-only register contains the value 104Ch, which is the vendor ID assigned to Texas
Instruments.
PCI register offset:
Register type:
00h
Read only
104Ch
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
4.3.3 Device ID Register
This 16-bit read-only register contains the device ID assigned by TI to the XIO3130. The value in this
register is the same for all downstream ports, as defined in the following table.
PCI register offset:
Register type:
02h
Read only
8233h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
4.3.4 Command Register
The Command register controls the way the downstream port bridge behaves on its primary interface; i.e.,
the internal PCI bus between the upstream and downstream ports.
PCI register offset:
Register type:
04h
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
88
XIO3130 Configuration Register Space
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