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NE5532PSE4 参数 Datasheet PDF下载

NE5532PSE4图片预览
型号: NE5532PSE4
PDF下载: 下载PDF文件 查看货源
内容描述: [DUAL OP-AMP, 5000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, PLASTIC, SO-8]
分类和应用: 放大器光电二极管
文件页数/大小: 142 页 / 1062 K
品牌: TI [ TEXAS INSTRUMENTS ]
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XIO3130  
www.ti.com  
SLLS693FMAY 2007REVISED JANUARY 2010  
Table 4-52. Bit Descriptions – Command Register  
BIT  
FIELD NAME  
ACCESS  
DESCRIPTION  
Reserved. When read, these bits return zeros.  
15:11  
RSVD  
r
INTx disable. This bit is used to enable device-specific INTx interrupts. The XIO3130  
downstream ports can generate INTx interrupts due to PCI Hot Plug events. The XIO3130  
forwards INTx messages from downstream ports to the upstream port (see INTx Support  
section) regardless of this bit.  
10  
9
INT_DISABLE  
FBB_ENB  
rw  
r
Fast back-to-back enable. This bit does not apply to PCI-Express, so it returns zero when read.  
SERR enable. The relevant error checking is unnecessary for the XIO3130 internal PCI bus.  
When set, this bit enables the transmission by the primary interface of ERR_NONFATAL and  
ERR_FATAL messages forwarded from the secondary interface. This bit does not affect  
transmission of ERR_COR messages.  
8
SERR_ENB  
rw  
7
6
STEP_ENB  
PERR_ENB  
r
Address/data stepping control. This bit does not apply to PCI-Express and is hardwired to 0.  
Parity error response enable. This bit has no impact on hardware behavior. It is assumed that  
the relevant error checking is unnecessary for the XIO3130 internal PCI bus.  
rw  
VGA palette snoop enable. The XIO3130 does not support VGA palette snooping, so this bit  
returns zero when read.  
5
VGA_ENB  
r
Memory write and invalidate enable. This bit does not apply to PCI-Express, so it is hardwired to  
zero.  
4
3
MWI_ENB  
SPECIAL  
r
r
Special cycle enable. This bit does not apply to PCI-Express and is hardwired to zero.  
Bus master enable. When set, the XIO3130 is enabled to initiate cycles on the downstream PCI  
Express interface.  
0 – Downstream PCI Express interface cannot initiate transactions. The XIO3130 must  
disable response to memory and I/O transactions on the downstream interface.  
2
MASTER_ENB  
rw  
1 – Downstream PCI Express interface can initiate transactions. The bridge can forward  
memory and I/O transactions.  
Memory response enable. Setting this bit enables the downstream port to respond to memory  
transactions.  
1
0
MEMORY_ENB  
IO_ENB  
rw  
rw  
I/O space enable. Setting this bit enables the downstream port to respond to I/O transactions.  
4.3.5 Status Register  
The Status register provides information about the downstream port’s primary interface, i.e., the internal  
PCI bus between the upstream and downstream ports.  
PCI register offset:  
Register type:  
06h  
Read Only; Clear by a Write of One; Hardware Update  
0010h  
Default value:  
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-53. Bit Descriptions – Status Register  
BIT  
FIELD NAME  
ACCESS  
DESCRIPTION  
Detected parity error. This bit is set when the virtual internal PCI interface receives a  
poisoned TLP. This bit is set regardless of the state of the Parity Error Response bit in the  
Command register.  
15  
14  
PAR_ERR  
rcu  
0 – No parity error detected.  
1 – Parity error detected.  
Signaled system error. This bit is set when the XIO3130 sends an ERR_FATAL or  
ERR_NONFATAL message upstream and the SERR Enable bit in the Command register is  
set.  
SYS_ERR  
rcu  
0 – No error signaled.  
1 – ERR_FATAL or ERR_NONFATAL signaled.  
Copyright © 2007–2010, Texas Instruments Incorporated  
XIO3130 Configuration Register Space  
89  
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Product Folder Link(s): XIO3130