XIO3130
SLLS693F–MAY 2007–REVISED JANUARY 2010
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Table 4-45. Uncorrectable Error Mask Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Malformed TLP mask.
18
MAL_TLP_MASK
rwh
0 - Error condition is unmasked.
1 - Error condition is masked.
Receiver Overflow mask.
17
16
15
14
13
RX_OVERFLOW_MASK
UNXP_CPL_MASK
rwh
rwh
rwh
rwh
rwh
0 - Error condition is unmasked.
1 - Error condition is masked.
Unexpected Completion mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
Completer Abort mask.
CPL_ABORT_MASK
CPL_TIMEOUT_MASK
FC_ERROR_MASK
0 - Error condition is unmasked.
1 - Error condition is masked.
Completion Timeout mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
Flow Control error mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
Poisoned TLP mask.
12
11:6
5
PSN_TLP_MASK
RSVD
rwh
r
0 - Error condition is unmasked.
1 - Error condition is masked.
Reserved. Return zeros when read.
Surprise Down error mask.
SD_MASK
rwh
0 - Error condition is unmasked.
1 - Error condition is masked.
Data Link Protocol error mask.
0 - Error condition is unmasked.
1 - Error condition is masked.
4
DLL_ERROR_MASK
rwh
3:1
0
RSVD
r
r
Reserved. Return zeros when read.
The value read from this bit is undefined.
Undefined
4.2.80 Uncorrectable Error Severity Register
The Uncorrectable Error Severity register controls the reporting of individual errors as ERR_FATAL or
ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is
clear, the corresponding error condition is identified as nonfatal.
PCI register offset:
Register type:
10Ch
Read Only, Read/Write
0003 2030h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
82
XIO3130 Configuration Register Space
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