XIO3130
SLLS693F–MAY 2007–REVISED JANUARY 2010
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Table 4-37. Bit Descriptions – GPIO C Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
GPIO 10 Control. This field controls the GPIO10 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_BTN0
011 – Port 2 ACT_BTN1
100 – Port 1 PWRFLT0
101 – Port 2 PWRFLT1
2:0
PCIE_GPIO10_CTL
rw
110 – Port 1 MRLS_DET0
111 – Port 2 MRLS_DET1
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
If the DN3_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO10
terminal is directly mapped as the PWR_GOOD PCI Hot Plug terminal for port 3 and is no
longer available for use as a GPIO. In this situation these bits have no meaning and should
be left at their default value.
4.2.64 GPIO D Control Register
This register is used to control the function of the PCIE_GPIO 15–19 pins.
PCI register offset:
Register type:
C2h
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
70
XIO3130 Configuration Register Space
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