欢迎访问ic37.com |
会员登录 免费注册
发布采购

NE5532PSE4 参数 Datasheet PDF下载

NE5532PSE4图片预览
型号: NE5532PSE4
PDF下载: 下载PDF文件 查看货源
内容描述: [DUAL OP-AMP, 5000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, PLASTIC, SO-8]
分类和应用: 放大器光电二极管
文件页数/大小: 142 页 / 1062 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号NE5532PSE4的Datasheet PDF文件第80页浏览型号NE5532PSE4的Datasheet PDF文件第81页浏览型号NE5532PSE4的Datasheet PDF文件第82页浏览型号NE5532PSE4的Datasheet PDF文件第83页浏览型号NE5532PSE4的Datasheet PDF文件第85页浏览型号NE5532PSE4的Datasheet PDF文件第86页浏览型号NE5532PSE4的Datasheet PDF文件第87页浏览型号NE5532PSE4的Datasheet PDF文件第88页  
XIO3130  
SLLS693FMAY 2007REVISED JANUARY 2010  
www.ti.com  
BIT NUMBER  
RESET STATE  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-47. Correctable Error Status Register  
BIT  
FIELD NAME  
ACCESS  
DESCRIPTION  
31:14  
13  
RSVD  
r
Reserved. Return zeroes when read.  
Advisory nonfatal error status.  
ANFES  
rcuh  
Replay timer timeout. This bit is asserted when the replay timer expires for a pending  
request or completion that has not been acknowledged.  
12  
11:9  
8
REPLAY_TMOUT  
RSVD  
rcuh  
r
Reserved. Return zeroes when read.  
REPLAY_NUM rollover. This bit is asserted when the replay counter rolls over when a  
pending request of completion has not been acknowledged.  
REPLAY_ROLL  
rcuh  
Bad DLLP error. This bit is asserted when an 8b/10n error is detected by the PHY during  
reception of a DLLP.  
7
BAD_DLLP  
rcuh  
Bad TLP error. This bit is asserted when an 8b/10b error is detected by the PHY during  
reception of a TLP.  
6
5:1  
0
BAD_TLP  
RSVD  
rcuh  
r
Reserved. Return zeros when read.  
Receiver error. This bit is asserted when an 8b/10b error is detected by the PHY at any  
time.  
RX_ERROR  
rcuh  
4.2.82 Correctable Error Mask Register  
The Correctable Error Mask register controls the reporting of individual errors as they occur. When a bit is  
set to one, error status bits are still affected, but the error is not logged and no error reporting message is  
sent upstream.  
PCI register offset:  
Register type:  
114h  
Read Only, Read/Write  
0000 2000h  
Default value:  
BIT NUMBER  
RESET STATE  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-48. Correctable Error Mask Register  
BIT  
FIELD NAME  
ACCESS  
DESCRIPTION  
Reserved. Return zeros when read.  
31:14  
RSVD  
r
Advisory nonfatal error mask. This bit is set by default to enable compatibility with  
software that does not comprehend role-based error reporting.  
13  
ANFEM  
rwh  
0 – Error condition is unmasked  
1 – Error condition is masked  
Replay timer timeout mask.  
12  
REPLAY_TMOUT_MASK  
RSVD  
rwh  
r
0 – Error condition is unmasked  
1 – Error condition is masked  
Reserved. Return zeros when read.  
11:9  
84  
XIO3130 Configuration Register Space  
Copyright © 2007–2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): XIO3130