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NE5532PSE4 参数 Datasheet PDF下载

NE5532PSE4图片预览
型号: NE5532PSE4
PDF下载: 下载PDF文件 查看货源
内容描述: [DUAL OP-AMP, 5000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, PLASTIC, SO-8]
分类和应用: 放大器光电二极管
文件页数/大小: 142 页 / 1062 K
品牌: TI [ TEXAS INSTRUMENTS ]
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XIO3130  
SLLS693FMAY 2007REVISED JANUARY 2010  
www.ti.com  
4.3.11 Primary Bus Number  
This register specifies the bus number of the PCI bus segment for the downstream port primary interface  
(i.e., the internal PCI bus).  
PCI register offset:  
Register type:  
18h  
Read/Write  
00h  
Default value:  
BIT NUMBER  
RESET STATE  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.12 Secondary Bus Number  
This register specifies the bus number of the PCI bus segment for the downstream port secondary  
interface (i.e., the PCI Express interface). The XIO3130 uses this register to determine how to respond to  
a Type 1 configuration transaction.  
PCI register offset:  
Register type:  
19h  
Read/Write  
00h  
Default value:  
BIT NUMBER  
RESET STATE  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.13 Subordinate Bus Number  
This register specifies the bus number of the highest number PCI bus segment that is downstream of the  
XIO3130 downstream port. The XIO3130 uses this register to determine how to respond to a Type 1  
configuration transaction.  
PCI register offset:  
Register type:  
1Ah  
Read/Write  
00h  
Default value:  
BIT NUMBER  
RESET STATE  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.14 Secondary Latency Timer Register  
This register does not apply to PCI-Express, so it is hardwired to zero.  
PCI register offset:  
Register type:  
1Bh  
Read only  
00h  
Default value:  
BIT NUMBER  
RESET STATE  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
92  
XIO3130 Configuration Register Space  
Copyright © 2007–2010, Texas Instruments Incorporated  
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Product Folder Link(s): XIO3130