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SPRS174S – APRIL 2001 – REVISED MARCH 2011
List of Tables
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
Hardware Features
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Signal Descriptions
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...........................................................................
Addresses of Flash Sectors in F2810
.........................................................................................
Wait States
........................................................................................................................
Boot Mode Selection
.............................................................................................................
Impact of Using the Code Security Module
...................................................................................
Peripheral Frame 0 Registers
..................................................................................................
Peripheral Frame 1 Registers
..................................................................................................
Peripheral Frame 2 Registers
..................................................................................................
Device Emulation Registers
.....................................................................................................
XINTF Configuration and Control Register Mappings
.......................................................................
XREVISION Register Bit Definitions
...........................................................................................
PIE Peripheral Interrupts
........................................................................................................
PIE Configuration and Control Registers
......................................................................................
External Interrupts Registers
...................................................................................................
PLL, Clocking, Watchdog, and Low-Power Mode Registers
...............................................................
PLLCR Register Bit Definitions
.................................................................................................
Possible PLL Configuration Modes
............................................................................................
F281x and C281x Low-Power Modes
.........................................................................................
CPU-Timers 0, 1, 2 Configuration and Control Registers
...................................................................
Module and Signal Names for EVA and EVB
................................................................................
EVA Registers
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ADC Registers
....................................................................................................................
3.3-V eCAN Transceivers for the TMS320F281x and TMS320C281x DSPs
............................................
CAN Registers
....................................................................................................................
McBSP Registers
.................................................................................................................
SCI-A Registers
..................................................................................................................
SCI-B Registers
..................................................................................................................
SPI Registers
.....................................................................................................................
GPIO Mux Registers
.............................................................................................................
GPIO Data Registers
............................................................................................................
TMS320x281x Peripheral Selection Guide
...................................................................................
Addresses of Flash Sectors in F2812 and F2811
TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During
Low-Power Modes at 150-MHz SYSCLKOUT
...............................................................................
TMS320C281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During
Low-Power Modes at 150-MHz SYSCLKOUT
...............................................................................
Typical Current Consumption by Various Peripherals (at 150 MHz)
......................................................
Recommended “Low-Dropout Regulators”
....................................................................................
....................................................
Input Clock Frequency
.........................................................................................................
XCLKIN Timing Requirements – PLL Bypassed or Enabled
.............................................................
XCLKIN Timing Requirements – PLL Disabled
............................................................................
Possible PLL Configuration Modes
...........................................................................................
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
......................................................
Reset (XRS) Timing Requirements
..........................................................................................
IDLE Mode Timing Requirements
...........................................................................................
TMS320F281x and TMS320C281x Clock Table and Nomenclature
List of Tables
7
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