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SPRS174S – APRIL 2001 – REVISED MARCH 2011
Table 6-2. TMS320C281x Current Consumption by Power-Supply Pins Over Recommended Operating
Conditions During Low-Power Modes at 150-MHz SYSCLKOUT
MODE
TEST CONDITIONS
All peripheral clocks are enabled. All PWM
pins are toggled at 100 kHz.
Data is continuously transmitted out of the
SCIA, SCIB, and CAN ports. The hardware
multiplier is exercised. Code is running out of
ROM with 5 wait-states.
•
•
•
•
•
•
•
(1)
(2)
(3)
(4)
XCLKOUT is turned off
All peripheral clocks are on, except ADC
Peripheral clocks are turned off
Pins without an internal PU/PD are tied
high/low
Peripheral clocks are turned off
Pins without an internal PU/PD are tied
high/low
Input clock is disabled
I
DD
TYP
MAX
(3)
TYP
I
DDIO (1)
MAX
(3)
TYP
I
DDA (2)
MAX
(3)
Operational
210 mA
(4)
260 mA
20 mA
30 mA
40 mA
50 mA
IDLE
140 mA
165 mA
20 mA
30 mA
5 µA
10 µA
STANDBY
5 mA
10 mA
5 µA
20 µA
5 µA
10 µA
HALT
70 µA
5 µA
10 µA
1 µA
I
DDIO
current is dependent on the electrical loading on the I/O pins.
I
DDA
includes current into V
DDA1
, V
DDA2
, AVDDREFBG, and V
DDAIO
pins.
MAX numbers are at 125°C, and MAX voltage (V
DD
= 1.89 V; V
DDIO
, V
DD3VFL
, V
DDA
= 3.47 V).
I
DD
represents the total current drawn from the 1.8-V rail (V
DD
). It includes a small amount of current (<1 mA) drawn by V
DD1
.
Copyright © 2001–2011, Texas Instruments Incorporated
Electrical Specifications
93
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