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SPRS174S – APRIL 2001 – REVISED MARCH 2011
The SPI port operation is configured and controlled by the registers listed in
Table 4-10. SPI Registers
(1)
NAME
SPICCR
SPICTL
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
(1)
ADDRESS
0x00 7040
0x00 7041
0x00 7042
0x00 7044
0x00 7046
0x00 7047
0x00 7048
0x00 7049
0x00 704A
0x00 704B
0x00 704C
0x00 704F
SIZE (x16)
1
1
1
1
1
1
1
1
1
1
1
1
SPI Operation Control Register
SPI Status Register
SPI Baud Rate Register
SPI Receive Emulation Buffer Register
SPI Serial Input Buffer Register
SPI Serial Output Buffer Register
SPI Serial Data Register
SPI FIFO Transmit Register
SPI FIFO Receive Register
SPI FIFO Control Register
SPI Priority Control Register
DESCRIPTION
SPI Configuration Control Register
These registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
Copyright © 2001–2011, Texas Instruments Incorporated
Peripherals
81
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