SPRS174S – APRIL 2001 – REVISED MARCH 2011
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6.4
Current Consumption
Table 6-1. TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating
Conditions During Low-Power Modes at 150-MHz SYSCLKOUT
MODE
TEST CONDITIONS
All peripheral clocks are enabled. All
PWM pins are toggled at 100 kHz.
Data is continuously transmitted out of
the SCIA, SCIB, and CAN ports. The
hardware multiplier is exercised. Code
is running out of flash with
5 wait-states.
•
•
•
•
•
•
•
•
•
•
(1)
(2)
(3)
(4)
Flash is powered down
XCLKOUT is turned off
All peripheral clocks are on,
except ADC
Flash is powered down
Peripheral clocks are turned off
Pins without an internal PU/PD are
tied high/low
Flash is powered down
Peripheral clocks are turned off
Pins without an internal PU/PD are
tied high/low
Input clock is disabled
I
DD
TYP
MAX
(3)
I
DDIO (1)
TYP
MAX
(3)
I
DD3VFL
TYP
MAX
(3)
I
DDA (2)
TYP
MAX
(3)
Operational
195 mA
(4)
230 mA
15 mA
30 mA
40 mA
45 mA
40 mA
50 mA
IDLE
125 mA
150 mA
5 mA
10 mA
2 µA
4 µA
1 µA
20 µA
STANDBY
5 mA
10 mA
5 µA
20 µA
2 µA
4 µA
1 µA
20 µA
HALT
70 µA
5 µA
20 µA
2 µA
4 µA
1 µA
20 µA
I
DDIO
current is dependent on the electrical loading on the I/O pins.
I
DDA
includes current into V
DDA1
, V
DDA2
, AVDDREFBG, and V
DDAIO
pins.
MAX numbers are at 125°C, and MAX voltage (V
DD
= 1.89 V; V
DDIO
, V
DD3VFL
, V
DDA
= 3.47 V).
I
DD
represents the total current drawn from the 1.8-V rail (V
DD
). It includes a small amount of current (<1 mA) drawn by V
DD1
.
NOTE
HALT and STANDBY modes cannot be used when the PLL is disabled.
92
Electrical Specifications
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