SPRS174S – APRIL 2001 – REVISED MARCH 2011
www.ti.com
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-47
6-48
EVBSOC Timing
................................................................................................................
External Interrupt Timing
.......................................................................................................
General-Purpose Output Timing
..............................................................................................
GPIO Input Qualifier – Example Diagram for QUALPRD = 1
.............................................................
General-Purpose Input Timing
................................................................................................
SPI Master Mode External Timing (Clock Phase = 0)
.....................................................................
SPI Master External Timing (Clock Phase = 1)
.............................................................................
SPI Slave Mode External Timing (Clock Phase = 0)
.......................................................................
SPI Slave Mode External Timing (Clock Phase = 1)
.......................................................................
Relationship Between XTIMCLK and SYSCLKOUT
.......................................................................
Example Read Access
.........................................................................................................
Example Write Access
.........................................................................................................
......................................................................
Example Read With Asynchronous XREADY Access
.....................................................................
Write With Synchronous XREADY Access
..................................................................................
Write With Asynchronous XREADY Access
................................................................................
External Interface Hold Waveform
............................................................................................
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
..................................................
ADC Analog Input Impedance Model
........................................................................................
ADC Power-Up Control Bit Timing
...........................................................................................
Sequential Sampling Mode (Single-Channel) Timing
......................................................................
Simultaneous Sampling Mode Timing
.......................................................................................
McBSP Receive Timing
........................................................................................................
McBSP Transmit Timing
.......................................................................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
...................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
...................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
...................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
...................................................
Example Read With Synchronous XREADY Access
6
List of Figures
Copyright © 2001–2011, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
