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TMS320F2812PGFS 参数 Datasheet PDF下载

TMS320F2812PGFS图片预览
型号: TMS320F2812PGFS
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号处理器 [Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 170 页 / 1662 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SPRS174S – APRIL 2001 – REVISED MARCH 2011
6.14.2 Output Clock Characteristics
Table 6-10. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
(1) (2)
NO.
C1
C3
C4
C5
C6
C7
(1)
(2)
(3)
(4)
t
c(XCO)
t
f(XCO)
t
r(XCO)
t
w(XCOL)
t
w(XCOH)
t
p
PARAMETER
Cycle time, XCLKOUT
Fall time, XCLKOUT
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
(4)
H–2
H–2
MIN
6.67
(3)
2
2
H+2
H+2
131072t
c(CI)
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
A load of 40 pF is assumed for these parameters.
H = 0.5t
c(XCO)
The PLL must be used for maximum frequency operation.
This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon.
C10
C8
XCLKIN
(A)
C9
C1
C3
C4
C6
C5
XCLKOUT
(A)(B)
A.
B.
The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in
is intended to illustrate the timing parameters only and may differ based on configuration.
XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-10. Clock Timing
6.15 Reset Timing
Table 6-11. Reset (XRS) Timing Requirements
(1)
MIN
t
w(RSL1)
t
w(RSL2)
t
w(WDRS)
t
d(EX)
t
OSCST (2)
t
su(XPLLDIS)
t
h(XPLLDIS)
t
h(XMP/MC)
t
h(boot-mode)
(1)
(2)
(3)
Pulse duration, stable XCLKIN to XRS high
Pulse duration, XRS low
Pulse duration, reset pulse generated by
watchdog
Delay time, address/data valid after XRS
high
Oscillator start-up time
Setup time for XPLLDIS pin
Hold time for XPLLDIS pin
Hold time for XMP/MC pin
Hold time for boot-mode pins
1
16t
c(CI)
16t
c(CI)
16t
c(CI)
2520t
c(CI) (3)
Warm reset
8t
c(CI)
8t
c(CI)
512t
c(CI)
32t
c(CI)
10
NOM
MAX
UNIT
cycles
cycles
cycles
cycles
ms
cycles
cycles
cycles
cycles
If external oscillator/clock source are used, reset time has to be low at least for 1 ms after V
DD
reaches 1.5 V.
Dependent on crystal/resonator and board design.
The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash. See the
TMS320x281x DSP Boot ROM Reference Guide
(literature number
and the
TMS320x281x DSP System Control and
Interrupts Reference Guide
(literature number
for further information.
Copyright © 2001–2011, Texas Instruments Incorporated
Electrical Specifications
103
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