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SPRS174S – APRIL 2001 – REVISED MARCH 2011
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in
Table 3-15. PLL, Clocking, Watchdog, and Low-Power Mode Registers
(1)
NAME
Reserved
Reserved
Reserved
HISPCP
LOSPCP
PCLKCR
Reserved
LPMCR0
LPMCR1
Reserved
PLLCR
SCSR
WDCNTR
Reserved
WDKEY
Reserved
WDCR
Reserved
(1)
(2)
ADDRESS
0x00 7010 – 0x00 7017
0x00 7018
0x00 7019
0x00 701A
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 701F
0x00 7020
0x00 7021
0x00 7022
0x00 7023
0x00 7024
0x00 7025
0x00 7026 – 0x00 7028
0x00 7029
0x00 702A – 0x00 702F
SIZE (x16)
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
6
Watchdog Control Register
Watchdog Reset Key Register
PLL Control Register
(2)
System Control and Status Register
Watchdog Counter Register
Low-Power Mode Control Register 0
Low-Power Mode Control Register 1
High-Speed Peripheral Clock Prescaler Register for
HSPCLK clock
Low-Speed Peripheral Clock Prescaler Register for
LSPCLK clock
Peripheral Clock Control Register
DESCRIPTION
All of the above registers can only be accessed by executing the EALLOW instruction.
The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio)
will not reset PLLCR.
Copyright © 2001–2011, Texas Instruments Incorporated
Functional Overview
49
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