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SPRS174S – APRIL 2001 – REVISED MARCH 2011
6.13 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the F281x and C281x DSPs.
lists the cycle times of various clocks.
Table 6-5. TMS320F281x and TMS320C281x Clock Table and Nomenclature
MIN
On chip oscillator clock
XCLKIN
SYSCLKOUT
XCLKOUT
HSPCLK
LSPCLK
ADC clock
SPI clock
McBSP
XTIMCLK
(1)
(2)
t
c(OSC)
, Cycle time
Frequency
t
c(CI)
, Cycle time
Frequency
t
c(SCO)
, Cycle time
Frequency
t
c(XCO)
, Cycle time
Frequency
t
c(HCO)
, Cycle time
Frequency
t
c(LCO)
, Cycle time
Frequency
t
c(ADCCLK)
, Cycle time
Frequency
t
c(SPC)
, Cycle time
Frequency
t
c(CKG)
, Cycle time
Frequency
t
c(XTIM)
, Cycle time
Frequency
6.67
150
50
20
50
20
(2)
NOM
MAX
50
35
250
150
500
150
2000
150
UNIT
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
28.6
20
6.67
4
6.67
2
6.67
0.5
6.67
13.3
40
13.3
(1)
75
26.6
(1)
(1)
150
75
25
37.5
(1)
This is the default reset value if SYSCLKOUT = 150 MHz.
The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be
SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.
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Electrical Specifications
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