TMS320F2812PGFS 参数 Datasheet PDF下载

SPRS174S – APRIL 2001 – REVISED MARCH 2011

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The SCI port operation is configured and controlled by the registers listed in

and

Table 4-8. SCI-A Registers

NAME

SCICCRA

SCICTL1A

SCIHBAUDA

SCILBAUDA

SCICTL2A

SCIRXSTA

SCIRXEMUA

SCIRXBUFA

SCITXBUFA

SCIFFTXA

SCIFFCTA

SCIPRIA

(1)

(1)

ADDRESS

0x00 7050

0x00 7051

0x00 7052

0x00 7053

0x00 7054

0x00 7055

0x00 7056

0x00 7057

0x00 7059

0x00 705A

0x00 705B

0x00 705C

0x00 705F

SIZE (x16)

1

1

1

1

1

1

1

1

1

1

1

1

1

SCI-A Control Register 1

SCI-A Baud Register, High Bits

SCI-A Baud Register, Low Bits

SCI-A Control Register 2

SCI-A Receive Status Register

DESCRIPTION

SCI-A Communications Control Register

SCI-A Receive Emulation Data Buffer Register

SCI-A Receive Data Buffer Register

SCI-A Transmit Data Buffer Register

SCI-A FIFO Transmit Register

SCI-A FIFO Receive Register

SCI-A FIFO Control Register

SCI-A Priority Control Register

SCIFFRXA

(1)

(1)

These registers are new registers for the FIFO mode.

Table 4-9. SCI-B Registers

(1)

NAME

SCICCRB

SCICTL1B

SCIHBAUDB

SCILBAUDB

SCICTL2B

SCIRXSTB

SCIRXEMUB

SCIRXBUFB

SCITXBUFB

SCIFFTXB

(2)

SCIFFRXB

SCIFFCTB

SCIPRIB

(1)

(2)

(2)

(2)

ADDRESS

0x00 7750

0x00 7751

0x00 7752

0x00 7753

0x00 7754

0x00 7755

0x00 7756

0x00 7757

0x00 7759

0x00 775A

0x00 775B

0x00 775C

0x00 775F

SIZE (x16)

1

1

1

1

1

1

1

1

1

1

1

1

1

SCI-B Control Register 1

SCI-B Baud Register, High Bits

SCI-B Baud Register, Low Bits

SCI-B Control Register 2

SCI-B Receive Status Register

DESCRIPTION

SCI-B Communications Control Register

SCI-B Receive Emulation Data Buffer Register

SCI-B Receive Data Buffer Register

SCI-B Transmit Data Buffer Register

SCI-B FIFO Transmit Register

SCI-B FIFO Receive Register

SCI-B FIFO Control Register

SCI-B Priority Control Register

Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

These registers are new registers for the FIFO mode.

78

Peripherals

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