SPRS174S – APRIL 2001 – REVISED MARCH 2011
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6.14 Clock Requirements and Characteristics
6.14.1 Input Clock Requirements
The clock provided at the XCLKIN pin generates the internal CPU clock cycle.
Table 6-6. Input Clock Frequency
PARAMETER
Resonator
f
x
Input clock frequency
Crystal
XCLKIN
f
l
Limp mode clock frequency
Without PLL
With PLL
MIN
20
20
4
5
2
TYP
MAX
35
35
150
100
MHz
MHz
UNIT
Table 6-7. XCLKIN Timing Requirements – PLL Bypassed or Enabled
NO.
C8
C9
C10
C11
C12
t
c(CI)
t
f(CI)
t
r(CI)
t
w(CIL)
t
w(CIH)
Cycle time, XCLKIN
Fall time, XCLKIN
Rise time, XCLKIN
Pulse duration, X1/XCLKIN low as a percentage of t
c(CI)
Pulse duration, X1/XCLKIN high as a percentage of t
c(CI)
40
40
MIN
6.67
MAX
250
6
6
60
60
UNIT
ns
ns
ns
%
%
Table 6-8. XCLKIN Timing Requirements – PLL Disabled
NO.
C8
C9
C10
C11
C12
t
c(CI)
t
f(CI)
t
r(CI)
t
w(CIL)
t
w(CIH)
Cycle time, XCLKIN
Fall time, XCLKIN
Rise time, XCLKIN
Pulse duration, X1/XCLKIN low as a percentage of t
c(CI)
Pulse duration, X1/XCLKIN high as a percentage of t
c(CI)
Up to 30 MHz
30 MHz to 150 MHz
Up to 30 MHz
30 MHz to 150 MHz
XCLKIN
≤
120 MHz
120 < XCLKIN
≤
150 MHz
XCLKIN
≤
120 MHz
120 < XCLKIN
≤
150 MHz
40
45
40
45
MIN
6.67
MAX
250
6
2
6
2
60
55
60
55
%
%
ns
UNIT
ns
ns
Table 6-9. Possible PLL Configuration Modes
PLL MODE
PLL Disabled
REMARKS
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled.
Clock input to the CPU (CLKIN) is directly derived from the clock signal present at
the X1/XCLKIN pin.
Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is
bypassed. However, the /2 module in the PLL block divides the clock input at the
X1/XCLKIN pin by two before feeding it to the CPU.
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module in the
PLL block now divides the output of the PLL by two before feeding it to the CPU.
SYSCLKOUT
XCLKIN
PLL Bypassed
PLL Enabled
XCLKIN/2
(XCLKIN * n) / 2
102
Electrical Specifications
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