SPRS174S – APRIL 2001 – REVISED MARCH 2011
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The CAN registers listed in
are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 4-6. CAN Registers
(1)
NAME
CANME
CANMD
CANTRS
CANTRR
CANTA
CANAA
CANRMP
CANRML
CANRFP
CANGAM
CANMC
CANBTC
CANES
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
(1)
ADDRESS
0x00 6000
0x00 6002
0x00 6004
0x00 6006
0x00 6008
0x00 600A
0x00 600C
0x00 600E
0x00 6010
0x00 6012
0x00 6014
0x00 6016
0x00 6018
0x00 601A
0x00 601C
0x00 601E
0x00 6020
0x00 6022
0x00 6024
0x00 6026
0x00 6028
0x00 602A
0x00 602C
0x00 602E
0x00 6030
0x00 6032
SIZE (x32)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Mailbox enable
Mailbox direction
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
Bit-timing configuration
Error and status
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
RX I/O control
Time stamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
DESCRIPTION
These registers are mapped to Peripheral Frame 1.
72
Peripherals
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