SPRS174S – APRIL 2001 – REVISED MARCH 2011
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The XINTF consists of five independent zones. One zone has its own chip select and the remaining four
zones share two chip selects. Each zone can be programmed with its own timing (wait states) and to
either sample or ignore external ready signal. This makes interfacing to external peripherals easy and
glueless.
NOTE
The chip selects of XINTF Zone 0 and Zone 1 are merged into a single chip select
(XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged into a single
chip select (XZCS6AND7). See
External Interface, XINTF (2812 only), for
details.
Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together to enable these blocks
to be “write/read peripheral block protected”. The “protected” mode ensures that all accesses to these
blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to
different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause
problems in certain peripheral applications where the user expected the write to occur first (as written).
The C28x CPU supports a block protection mode where a region of memory can be protected to make
sure that operations occur as written (the penalty is extra cycles that are added to align the operations).
This mode is programmable and, by default, it will protect the selected zones.
On the 2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects
microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high
memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In
microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows
the user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on
reset is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in
software and hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are
affected by XMP/MC.
I/O space is not supported on the 2812 XINTF.
The wait states for the various spaces in the memory map area are listed in
Table 3-3. Wait States
AREA
M0 and M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
Peripheral Frame 2
L0 and L1 SARAMs
OTP (or ROM)
WAIT-STATES
0-wait
0-wait
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait
Programmable,
1-wait minimum
Programmable,
0-wait minimum
0-wait
1-wait
Programmable,
1-wait minimum
Fixed
Fixed
Fixed
Fixed
Fixed
Programmed via the Flash registers. 1-wait-state operation is possible at a
reduced CPU frequency. See
Flash (F281x Only), for more
information.
Programmed via the Flash registers. 0-wait-state operation is possible at
reduced CPU frequency. The CSM password locations are hardwired for
16 wait states. See
Flash (F281x Only), for more information.
Fixed
Fixed
Programmed via the XINTF registers.
Cycles can be extended by external memory or peripheral.
0-wait operation is not possible.
COMMENTS
Flash (or ROM)
H0 SARAM
Boot-ROM
XINTF
32
Functional Overview
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