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TMS320F2812PGFS 参数 Datasheet PDF下载

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型号: TMS320F2812PGFS
PDF下载: 下载PDF文件 查看货源
内容描述: 数字信号处理器 [Digital Signal Processors]
分类和应用: 数字信号处理器
文件页数/大小: 170 页 / 1662 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SPRS174S – APRIL 2001 – REVISED MARCH 2011
Table 3-16. PLLCR Register Bit Definitions
BIT(S)
15:4
NAME
Reserved
TYPE
R=0
XRS
RESET
(1)
0:0
SYSCLKOUT = (XCLKIN * n)/2, where n is the PLL multiplication
factor.
Bit Value
0000
0001
0010
0011
0100
0101
3:0
DIV
R/W
0,0,0,0
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
(1)
n
PLL Bypassed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SYSCLKOUT
XCLKIN/2
XCLKIN/2
XCLKIN
XCLKIN * 1.5
XCLKIN * 2
XCLKIN * 2.5
XCLKIN * 3
XCLKIN * 3.5
XCLKIN * 4
XCLKIN * 4.5
XCLKIN * 5
Reserved
Reserved
Reserved
Reserved
Reserved
DESCRIPTION
The PLLCR register is reset to a known state by the XRS reset line.
If a reset is issued by the debugger, the PLL clocking ratio is
not changed.
3.8.1
Loss of Input Clock
In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL will
still issue a “limp-mode” clock. The limp-mode clock will continue to clock the CPU and peripherals at a
typical frequency of 1–4 MHz. The PLLCR register should have been written to with a non-zero value for
this feature to work.
Normally, when the input clocks are present, the watchdog counter will decrement to initiate a watchdog
reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter will stop
decrementing (i.e., the watchdog counter does not change with the limp-mode clock). This condition could
be used by the application firmware to detect the input clock failure and initiate necessary shut-down
procedure for the system.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical must
implement a mechanism by which the DSP will be held in reset, should the input clocks ever
fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP, should the
capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a
periodic basis to prevent it from getting fully charged. Such a circuit would also help in
detecting failure of the V
DD3VFL
rail.
Copyright © 2001–2011, Texas Instruments Incorporated
Functional Overview
51
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