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SPRS174S – APRIL 2001 – REVISED MARCH 2011
6.16 Low-Power Mode Wakeup Timing
Table 6-12. IDLE Mode Timing Requirements
MIN
t
w(WAKE-INT)
(1)
Pulse duration, external wake-up signal
Without input qualifier
With input qualifier
2t
c(SCO)
1t
c(SCO)
+ IQT
(1)
NOM
MAX
UNIT
cycles
Input Qualification Time (IQT) = [t
c(SCO)
× 2 × QUALPRD] × 5 + [t
c(SCO)
× 2 × QUALPRD].
Table 6-13. IDLE Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
(1)
(2)
MIN
TYP
MAX
8t
c(SCO)
8t
c(SCO)
+ IQT
(2)
1050t
c(SCO)
1050t
c(SCO)
+ IQT
(2)
8t
c(SCO)
8t
c(SCO)
+ IQT
(2)
UNIT
Delay time, external wake signal to program execution resume
(1)
•
t
d(WAKE-IDLE)
•
•
Wake-up from Flash
– Flash module in active state
Wake-up from Flash
– Flash module in sleep state
Wake-up from SARAM
cycles
cycles
cycles
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up) signal involves additional latency.
Input Qualification Time (IQT) = [t
c(SCO)
× 2 × QUALPRD] × 5 + [t
c(SCO)
× 2 × QUALPRD].
t
d(WAKE-IDLE)
A0-A15
XCLKOUT
(A)
t
w(WAKE-INT)
WAKE INT
(B)
A.
B.
XCLKOUT = SYSCLKOUT
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-15. IDLE Entry and Exit Timing
Copyright © 2001–2011, Texas Instruments Incorporated
Electrical Specifications
107
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