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    CL-PD6833-QC-A 参数 Datasheet PDF下载

    CL-PD6833-QC-A图片预览
    型号： CL-PD6833-QC-A
    PDF下载： 下载PDF文件 查看货源
    内容描述： PCI到CardBus主机适配器 [PCI-to-CardBus Host Adapter]
    分类和应用： 总线控制器微控制器和处理器外围集成电路数据传输PC时钟
    文件页数/大小： 216 页 / 1799 K
    品牌： CIRRUS [ CIRRUS LOGIC ]
     浏览型号CL-PD6833-QC-A的Datasheet PDF文件第1页浏览型号CL-PD6833-QC-A的Datasheet PDF文件第2页浏览型号CL-PD6833-QC-A的Datasheet PDF文件第3页浏览型号CL-PD6833-QC-A的Datasheet PDF文件第5页浏览型号CL-PD6833-QC-A的Datasheet PDF文件第6页浏览型号CL-PD6833-QC-A的Datasheet PDF文件第7页浏览型号CL-PD6833-QC-A的Datasheet PDF文件第8页浏览型号CL-PD6833-QC-A的Datasheet PDF文件第9页  
    CL-PD6833
    PCI-to-CardBus Host Adapter
    6.
    CARDBUS REGISTERS ...................................................................................................... 75
    6.1
    6.2
    6.3
    6.4
    6.5
    Status Event — PME_CXT .................................................................................................................. 75
    Status Mask — PME_CXT................................................................................................................... 77
    Present State ....................................................................................................................................... 78
    Event Force .......................................................................................................................................... 80
    Control — PME_CXT ........................................................................................................................... 82
    Index .................................................................................................................................................... 85
    Data...................................................................................................................................................... 90
    Chip Revision ....................................................................................................................................... 91
    Interface Status .................................................................................................................................... 92
    Power Control — PME _CXT ............................................................................................................... 94
    Interrupt and General Control — PME_CXT........................................................................................ 96
    Card Status Change — PME_CXT ...................................................................................................... 98
    Management Interrupt Configuration — PME_CXT............................................................................. 99
    Mapping Enable .................................................................................................................................101
    I/O Window Mapping Registers..........................................................................................................105
    9.1.1 I/O Window Control ...............................................................................................................105
    9.1.2 System I/O Map 0–1 Start Address Low ...............................................................................107
    9.1.3 System I/O Map 0–1 Start Address High ..............................................................................107
    9.1.4 System I/O Map 0–1 End Address Low ................................................................................108
    9.1.5 System I/O Map 0–1 End Address High ...............................................................................108
    9.1.6 Card I/O Map 0–1 Offset Address Low .................................................................................109
    9.1.7 Card I/O Map 0–1 Offset Address High ................................................................................109
    Memory Window Mapping Registers .................................................................................................110
    9.2.1 System Memory Map 0–4 Start Address Low.......................................................................110
    9.2.2 System Memory Map 0–4 Start Address High......................................................................111
    9.2.3 System Memory Map 0–4 End Address Low ........................................................................112
    9.2.4 System Memory Map 0–4 End Address High .......................................................................113
    9.2.5 Card Memory Map 0–4 Offset Address Low .........................................................................114
    9.2.6 Card Memory Map 0–4 Offset Address High ........................................................................115
    7.
    OPERATION REGISTERS ................................................................................................... 85
    7.1
    7.2
    8.
    DEVICE CONTROL REGISTERS........................................................................................ 91
    8.1
    8.2
    8.3
    8.4
    8.5
    8.6
    8.7
    9.
    WINDOW MAPPING REGISTERS..................................................................................... 103
    9.1
    9.2
    10. GENERAL WINDOW MAPPING REGISTERS.................................................................. 117
    10.1 General Mapping Registers for I/O Mode ..........................................................................................119
    10.1.1 Gen Map 0–6 Start Address Low (I/O)..................................................................................119
    10.1.2 Gen Map 0–6 Start Address High (I/O).................................................................................120
    10.1.3 Gen Map 0–6 End Address Low (I/O) ...................................................................................121
    10.1.4 Gen Map 0–6 End Address High (I/O) ..................................................................................122
    10.1.5 Gen Map 0–6 Offset Address Low (I/O)................................................................................123
    10.1.6 Gen Map 0–6 Offset Address High (I/O) ...............................................................................124
    10.2 General Mapping Register for Memory Mode ....................................................................................125
    10.2.1 Gen Map 0–6 Start Address Low (Memory) .........................................................................125
    10.2.2 Gen Map 0–6 Start Address High (Memory).........................................................................126
    10.2.3 Gen Map 0–6 End Address Low (Memory)...........................................................................127
    10.2.4 Gen Map 0–6 End Address High (Memory)..........................................................................128
    10.2.5 Gen Map 0–6 Offset Address Low (Memory)........................................................................129
    10.2.6 Gen Map 0–6 Offset Address High (Memory).......................................................................130
    4
    TABLE OF CONTENTS
    ADVANCE DATA BOOK v0.3
    June 1998

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