CL-PD6833
PCI-to-CardBus Host Adapter
9.2.4
System Memory Map 0–4 End Address High
Register Name: System Memory Map 0–4 End Address High
Register Per: socket
Register Compatibility Type: 365
I/O Index: 13h, 1Bh, 23h, 2Bh, 33h
Memory Offset: 813h, 81Bh, 823h, 82Bh, 833h
Bit 7
Bit 6
Bit 5
Scratchpad Bits
R/W:00
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Card Timer Select
R/W:00
End Address 23:20
R/W:0000
There are five separate System Memory Map End Address High registers, each with identical fields.
These registers are located at the following indexes:
Index (Socket A)
Register
13h
1Bh
23h
2Bh
33h
System Memory Map 0 End Address High
System Memory Map 1 End Address High
System Memory Map 2 End Address High
System Memory Map 3 End Address High
System Memory Map 4 End Address High
Bits 3:0 — End Address 23:20
This field contains the most-significant four bits of the End Address. See the description of the End
Address field associated with bits 7:0 of the System Memory Map 0–4 End Address Low
register. Note that the upper memory addresses are stored in the System Memory Map Upper
Address register.
Bits 5:4 — Scratchpad Bits
Bits 7:6 — Card Timer Select
Bit 7
Bit 6
Timer Set Select
Selects Timer Set 0
Selects Timer Set 1
Selects Timer Set 1
Selects Timer Set 1
0
0
1
1
0
1
0
1
This field selects theTimer Set registers to control socket timing for card accesses in this window
address range. This field selects the timer set. Timer Set 0 and 1 reset to values compatible with
PC Card standards. Mapping of bits 7:6 to Timer Set 0 and 1, as shown, is done for software
compatibility with other older ISA-bus based PC Card host adapters that use ISA bus wait states
instead of Timer Set registers.
June 1998
113
ADVANCE DATA BOOK v0.3
WINDOW MAPPING REGISTERS
CIRRUS [ CIRRUS LOGIC ]
