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CL-PD6833-QC-A 参数 Datasheet PDF下载

CL-PD6833-QC-A图片预览
型号: CL-PD6833-QC-A
PDF下载: 下载PDF文件 查看货源
内容描述: PCI到CardBus主机适配器 [PCI-to-CardBus Host Adapter]
分类和应用: 总线控制器微控制器和处理器外围集成电路数据传输PC时钟
文件页数/大小: 216 页 / 1799 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CL-PD6833  
PCI-to-CardBus Host Adapter  
10.2.3  
Gen Map 0–6 End Address Low (Memory)  
Register Name: Gen Map 0–6 End Address Low (Memory)  
Register Per: socket  
Register Compatibility Type: 365  
I/O Index: 0Ah, 0Eh, 12h, 1Ah, 22h, 2Ah, 32h  
Memory Offset: 80Ah, 80Eh, 812h, 81Ah, 822h, 82Ah, 832h  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
End Address 19:12 (Memory)  
R/W:00000000  
There are seven separate Gen Map End Address Low registers, each with identical fields. These  
registers are located at the following indexes:  
Index  
Memory Offset  
Gen Map End Address Low  
Default Operation  
0Ah  
0Eh  
12h  
1Ah  
22h  
2Ah  
32h  
80Ah  
80Eh  
812h  
81Ah  
822h  
82Ah  
832h  
Gen Map 5 End Address Low  
Gen Map 6 End Address Low  
Gen Map 0 End Address Low  
Gen Map 1 End Address Low  
Gen Map 2 End Address Low  
Gen Map 3 End Address Low  
Gen Map 4 End Address Low  
I/O Window 0  
I/O Window 1  
Memory Window 0  
Memory Window 1  
Memory Window 2  
Memory Window 3  
Memory Window 4  
Bits 7:0 — End Address 19:12 (Memory)  
This register contains the least-significant byte of the address that specifies where in the Memory  
space corresponding to the Memory map ends. Memory accesses that are equal or below this  
address and equal or above the corresponding Gen Map Start Address are mapped into the I/O or  
memory space of the corresponding PC Card.  
The most-significant bits are located in the Gen Map 0–6 End Address High register.  
June 1998  
127  
ADVANCE DATA BOOK v0.3  
GENERAL WINDOW MAPPING  
REGISTERS