CL-PD6833
PCI-to-CardBus Host Adapter
7.
OPERATION REGISTERS
In I/O mode, the CL-PD6833 internal Device Control,Window Mapping, Extension, and Timing regis-
ters are accessed through a pair of Operation registers — an Index register and a Data register.
The Index register is accessed at the address that is programmed in the I/O Base Address register, and
the Data register (see page 90) is accessed by adding 1 to the programmed address in the I/O Base
Address register.
Sockets 0–3
Data to/from
Indexed Register
Ignored
Ignored
Index Register
3 + I/O Base Address
2 + I/O Base Address 1 + I/O Base Address
I/O Base Address
Figure 7-1. Operation Registers as PCI Doubleword I/O Space at I/O Base Address Register
(Programmed at Configuration Space, Offset 44h)
7.1
Index
Register Name: Index
I/O Index: n/a
Register Per: chip
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Register Index
R/W:000000
Bit 2
Bit 1
Bit 0
Socket Index
R/W:00
Bits 5:0 — Register Index
These bits determine which of the 64 possible socket-specific registers are accessed when the
Data register is next accessed by the processor. Note that some values of the Register Index field
are reserved (see Table 7-1 on page 86).
Bits 7:6 — Socket Index
These bits determine which set of socket-specific registers are selected.
The Index register value determines which internal register should be accessed (read or written)
in response to each CPU access of the Data register. Each of the two possible PC Card sockets
is allocated 64 of the 256 locations in the internal register index space.
FFh
80h
7Fh
Socket B Registers
40h
3Fh
Socket A Registers
00h
Figure 7-2. Socket and Register Index Space
June 1998
85
ADVANCE DATA BOOK v0.3
OPERATION REGISTERS
CIRRUS [ CIRRUS LOGIC ]
