CL-PD6833
PCI-to-CardBus Host Adapter
10.2.5
Gen Map 0–6 Offset Address Low (Memory)
Register Name: Gen Map 0–6 Offset Address Low (Memory)
Register Per: socket
Register Compatibility Type: ext.
I/O Index: 14h, 1Ch, 24h, 2Ch, 34h, 36h, 38h
Memory Offset: 814h, 81Ch, 824h, 82Ch, 834h, 836h, 838h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 19:12 (Memory)
R/W:0000000
There are seven separate Gen Map Offset Address Low registers, each with identical fields. These
registers are located at the following indexes:
I/O Index
Memory Offset
Gen Map Offset Address Low
Default Operation
14h
1Ch
24h
2Ch
34h
36h
38h
814h
81Ch
824h
82Ch
834h
836h
838h
Gen Map 0 Offset Address Low
Gen Map 1 Offset Address Low
Gen Map 2 Offset Address Low
Gen Map 3 Offset Address Low
Gen Map 4 Offset Address Low
Gen Map 5 Offset Address Low
Gen Map 6 Offset Address Low
Memory Window 0
Memory Window 1
Memory Window 2
Memory Window 3
Memory Window 4
I/O Window 0
I/O Window 1
Bits 7:0 — Offset Address 19:12 (Memory)
This register contains the least-significant byte of the quantity that is added to the system
address that determines where in the PCMCIA card’s memory map the memory access occurs.
The most-significant bits are located in the Gen Map 0–6 Offset Address High register.
June 1998
129
ADVANCE DATA BOOK v0.3
GENERAL WINDOW MAPPING
REGISTERS
CIRRUS [ CIRRUS LOGIC ]
