CL-PD6833
PCI-to-CardBus Host Adapter
6.5
Control — PME_CXT
Register Name: Control — PME_CXT
Memory Offset: 010h
Register Per: socket
Bit 31
Bit 23
Bit 15
Bit 7
Bit 30
Bit 22
Bit 14
Bit 6
Bit 29
Bit 21
Bit 13
Bit 5
Bit 28
Bit 27
Bit 26
Bit 18
Bit 10
Bit 2
Bit 25
Bit 17
Bit 9
Bit 24
Bit 16
Bit 8
Byte 3
Reserved
R:00000000
Bit 20 Bit 19
Byte 2
Byte 1
Byte 0
Reserved
R:00000000
Bit 12
Bit 11
Reserved
R:00000000
Bit 4
Bit 3
Bit 1
Bit 0
Stop Clock
R/W:0
V
Control
Reserved
R:0
V
Control
CC
PP
R/W:000
R/W:000
NOTE: PME_CXT (PME Context) is a set of register bits that do not get reset or initialized if PME Enable is true
when the CL-PD6833 changes power states from D3 to D0 by a software PCI Bus Segment reset.
The Socket Control register provides control of the socket’s V and V . All bits in this register are set
CC
PP
to ‘0’ by RST# and power removed from the socket. This register is write-protected by writes to bits 13:10
of the Event Force register, and not write-protected on completion of the decoding sequence of the CD1,
CD2, VS1, and VS2 lines or completion of CV test. Use either this register or the Power Control register
(index 02h) for power control. Do not use both registers.
Bits 2:0 — V Control
PP
These bits are used to switch the V power using external V control logic.The CL-PD6833 has
PP
PP
no knowledge of a card’s V voltage requirement. Software must determine the needed voltage
PP
from the card’s CIS. The following table shows the V requested depending on the setting of the
PP
bits.
Bit 2
Bit 1
Bit 0
VPP Requested
0
0
0
0
0
0
1
0
1
0 V
12.0 V
5.0 V
0
1
1
3.3 V
100—111
Reserved
82
June 1998
CARDBUS REGISTERS
ADVANCE DATA BOOK v0.3
CIRRUS [ CIRRUS LOGIC ]
