CL-PD6833
PCI-to-CardBus Host Adapter
11. EXTENSION REGISTERS .................................................................................................131
11.1 Misc Control 1 ....................................................................................................................................132
11.2 FIFO Control ......................................................................................................................................134
11.3 Misc Control 2 ....................................................................................................................................136
11.4 Chip Information.................................................................................................................................137
11.5 ATA Control ........................................................................................................................................138
11.6 Extended Index ..................................................................................................................................140
11.7 Extended Data ...................................................................................................................................141
11.7.1 Extension Control 1...............................................................................................................142
11.7.2 Gen Map 0–6 Upper Address (Memory)...............................................................................143
11.7.3 Pin Multiplex Control 0 Register — PME_CXT .....................................................................144
11.7.4 Pin Multiplex Control 1 Register — PME_CXT .....................................................................146
11.7.5 GPIO Output Control.............................................................................................................147
11.7.6 GPIO Input Control................................................................................................................147
11.7.7 GPIO Output Data.................................................................................................................148
11.7.8 GPIO Input Data....................................................................................................................148
11.8 Prefetch Window Register..................................................................................................................149
11.8.1 PCI Space Control ................................................................................................................149
11.8.2 PC Card Space Control.........................................................................................................150
11.8.3 Window Type Select..............................................................................................................150
11.8.4 Misc Control 3 .......................................................................................................................151
11.8.5 SMBus Socket Power Control Address — PME_CXT ..........................................................153
11.8.6 Gen Map 0–6 Extra Control (I/O) ..........................................................................................154
11.8.7 Gen Map 0–6 Extra Control (Memory)..................................................................................155
11.8.8 Extension Card Status Change.............................................................................................156
11.8.9 Misc Control 4 .......................................................................................................................157
11.8.10 Misc Control 5 .......................................................................................................................158
11.8.11 Misc Control 6 .......................................................................................................................158
11.9 Device Identification and Implementation Scheme ............................................................................159
11.9.1 Mask Revision Byte...............................................................................................................159
11.9.2 Product ID Byte.....................................................................................................................160
11.9.3 Device Capability Byte A.......................................................................................................161
11.9.4 Device Capability Byte B.......................................................................................................162
11.9.5 Device Implementation Byte A..............................................................................................163
11.9.6 Device Implementation Byte B..............................................................................................164
11.9.7 Device Implementation Byte C..............................................................................................165
11.9.8 Device Implementation Byte D..............................................................................................166
12. TIMING REGISTERS...........................................................................................................167
12.1 Setup Timing 0–1 ...............................................................................................................................167
12.2 Command Timing 0–1........................................................................................................................168
12.3 Recovery Timing 0–1 .........................................................................................................................169
13. DMA OPERATION REGISTERS.........................................................................................171
13.1 Low Address ......................................................................................................................................172
13.2 Mid Low Address................................................................................................................................172
13.3 Mid High Address...............................................................................................................................173
13.4 High Address......................................................................................................................................173
13.5 Low Count..........................................................................................................................................174
13.6 Mid Count...........................................................................................................................................174
13.7 High Count .........................................................................................................................................174
June 1998
5
ADVANCE DATA BOOK v0.3
TABLE OF CONTENTS
CIRRUS [ CIRRUS LOGIC ]
