CL-PD6833
PCI-to-CardBus Host Adapter
8.6
Management Interrupt Configuration — PME_CXT
Register Name: Management Interrupt Configuration — PME_CXT
Register Per: socket
Register Compatibility Type: 365
I/O Index: 05h
Memory Offset: 805h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Battery Dead
Or Status
Change
Battery
Warning
Enable
Card Detect
Enable
Management IRQ
R/W:0000
Ready Enable
R/W:0
Enable
R/W:0
R/W:0
R/W:0
NOTE: PME_CXT (PME Context) is a set of register bits that do not get reset or initialized if PME Enable is true
when the CL-PD6833 changes power states from D3 to D0 through a software PCI Bus Segment reset.
This register controls which status changes cause management interrupts.They also control the pin loca-
tion where the management interrupts appear.
Bit 0 — Battery Dead Or Status Change Enable
0
1
Battery Dead Or Status Change management interrupt is disabled.
If the Battery Dead Or Status Change bit is ‘1’, a management interrupt occurs.
When this bit is ‘1’, a management interrupt occurs when the Card Status Change register’s Bat-
tery Dead Or Status Change bit (see page 98) is‘1’.This allows management interrupts to be gen-
erated on changes in level of the BVD1/STSCHG#/RI# pin.
Bit 1 — Battery Warning Enable
0
1
Battery Warning Change management interrupt is disabled.
If the Battery Warning Change bit is ‘1’, a management interrupt occurs.
When this bit is ‘1’, a management interrupt occurs if the Card Status Change register’s Battery
Warning Change bit (see page 98) is ‘1’. This allows management interrupts to be generated on
changes in level of the BVD2/SPKR#/LED# pin. This bit is not valid in I/O Card Interface mode.
Bit 2 — Ready Enable
0
Ready Change management interrupt is disabled.
If the Ready Change bit is ‘1’, a management interrupt occurs.
1
When this bit is ‘1’, a management interrupt occurs when the Card Status Change register’s
Ready Change bit (see page 98) is ‘1’. This allows management interrupts to be generated on
changes in level of the RDY/IREQ# pin.This bit is not valid in I/O Card Interface mode.This bit ap-
plies to Memory mode only.
Bit 3 — Card Detect Enable
0
Card Detect Change management interrupt is disabled.
If the Card Detect Change bit is ‘1’, a management interrupt occurs.
1
When this bit is ‘1’, a management interrupt occurs when the Card Status Change register’s Card
Detect Change bit (see page 98) is ‘1’. This allows management interrupts to be generated on
changes in level of the CD1# and CD2# pins.
June 1998
99
ADVANCE DATA BOOK v0.3
DEVICE CONTROL REGISTERS
CIRRUS [ CIRRUS LOGIC ]
