CL-PD6833
PCI-to-CardBus Host Adapter
9.1.6
Card I/O Map 0–1 Offset Address Low
Register Name: Card I/O Map 0–1 Offset Address Low
Register Per: socket
Register Compatibility Type: ext.
I/O Index: 36h, 38h
Memory Offset: 836h, 838h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Compatibility
Offset Address 7:1
R/W:0000000
a
Bit
R/W:0
a
This bit must be programmed to ‘0’. This compatibility bit does not affect I/O offset address.
There are two separate Card I/O Map Offset Address Low registers, each with identical fields. These
registers are located at the following indexes:
Index (Socket A)
Register
36h
38h
Card I/O Map 0 Offset Address Low
Card I/O Map 1 Offset Address Low
Bits 7:1 — Offset Address 7:1
This register contains the least-significant byte of the quantity that is added to the system I/O
address to determine where in the PC Card’s I/O map the I/O access occurs. The CL-PD6833
internally defines bit 0 of offset address as ‘0’.
The most-significant byte is located in the Card I/O Map 0–1 Offset Address High register.
Bit 0 — Compatibility Bit
This bit must be programmed to ‘0’. It does not affect the I/O offset address.
9.1.7
Card I/O Map 0–1 Offset Address High
Register Name: Card I/O Map 0–1 Offset Address High
I/O Index: 37h, 39h
Register Per: socket
Register Compatibility Type: ext.
Memory Offset: 837h, 839h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 15:8
R/W:00000000
There are two separate Card I/O Map Offset Address High registers, each with identical fields. These
registers are located at the following indexes:
Index (Socket A)
Card I/O Map Offset Address High
37h
39h
Card I/O Map 0 Offset Address High
Card I/O Map 1 Offset Address High
Bits 7:0 — Offset Address 15:8
This register contains the most-significant byte of the offset address. See the description of the
End Address field associated with bits 7:1 of the Card I/O Map 0–1 Offset Address Low register
(on page 109).
June 1998
109
ADVANCE DATA BOOK v0.3
WINDOW MAPPING REGISTERS
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