CL-PD6833
PCI-to-CardBus Host Adapter
6.4
Event Force
Register Name: Event Force
Memory Offset: 00Ch
Register Per: socket
Bit 31
Bit 30
Bit 29
Bit 21
Bit 28
Bit 27
Bit 26
Bit 18
Bit 25
Bit 17
Bit 9
Bit 24
Byte 3
Reserved
R:00000000
Bit 20 Bit 19
Bit 23
Bit 22
Bit 16
Byte 2
Byte 1
Byte 0
Reserved
R:00000000
Bit 15
Bit 14
Bit 13
Y-V
Bit 12
Bit 11
Bit 10
Bit 8
Bad V
CC
Reserved
CV Test
X-V
3.3-V Card
5-V Card
Data Lost
Request
W:0
W:0
W:0
W:0
W:0
W:0
W:0
W:0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CardBus PC 16-Bit PC
CCD2
Changed
CCD1
Changed
CSTSCHG/
WAKEUP
Not a Card
W:0
Reserved
W:0
Power Cycle
W:0
Card
Card
W:0
W:0
W:0
W:0
W:0
The Event Force register is a phantom register.These bits are merely control bits.They are not registered
and need no clearing. They provide software the ability to force various status and event bits in the
CL-PD6833.This gives software the ability to test and restore status.Writing ‘1’ to a bit in this register sets
the corresponding bit in the Status Event register and/or the Present State register. Bits 3:0 generate
Management Interrupt if the correct Mask bit is set.
Bit 0 — CSTSCHG/WAKEUP
This bit sets the Card Status Change bit in the Status Event register. The Present State register
remains unchanged.
Bit 1 — CCD1 Changed
This bit sets the CCD1 bit in the Status Event register. The Present State register remains
unchanged.
Bit 2 — CCD2 Changed
This bit sets the CCD2 bit in the Status Event register. The Present State register remains
unchanged.
Bit 3 — Power Cycle
This bit sets the Power Cycle bit in the Status Event register.The Present State register remains
unchanged.
Bit 4 — 16-Bit PC Card
This bit sets the 16-bit PC Card bit in the Present State register. If a card is installed in the socket,
writes to this bit are ignored.
80
June 1998
CARDBUS REGISTERS
ADVANCE DATA BOOK v0.3
CIRRUS [ CIRRUS LOGIC ]
