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PIC16F767-I/SP 参数 Datasheet PDF下载

PIC16F767-I/SP图片预览

型号：	PIC16F767-I/SP
PDF下载：	下载PDF文件查看货源
内容描述：	28 /40/ 44引脚， 8位CMOS闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用：	闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小：	276 页 / 4898 K
品牌：	MICROCHIP [ MICROCHIP TECHNOLOGY ]

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PIC16F7X7

SS ....................................................................................... 93

SSPBUF.............................................................................. 98

SSPIF Bit ............................................................................ 25

SSPOV.............................................................................. 123

SSPOV Status Flag .......................................................... 123

SSPSR ................................................................................ 98

SSPSTAT Register

R/W Bit...................................................................... 107

Stack ................................................................................... 29

Overflows .................................................................... 29

Underflows .................................................................. 29

Status Register

C Bit ............................................................................ 21

DC Bit.......................................................................... 21

IRP Bit......................................................................... 21

PD Bit.................................................................. 21, 172

TO Bit.................................................................. 21, 172

Z Bit............................................................................. 21

Synchronous Serial Port

Interrupt Flag Bit (SSPIF)........................................... 25

Timing Diagrams

A/D Conversion ........................................................ 236

Acknowledge Sequence ........................................... 126

Asynchronous Master Transmission ........................ 139

Asynchronous Master Transmission

(Back to Back) .................................................. 139

Asynchronous Reception.......................................... 140

Asynchronous Reception with

Address Byte First ............................................ 143

Asynchronous Reception with

Address Detect ................................................. 143

AUSART Synchronous Receive

(Master/Slave) .................................................. 234

AUSART Synchronous Transmission

(Master/Slave) .................................................. 234

Baud Rate Generator with Clock Arbitration............. 120

BRG Reset Due to SDA Arbitration

During Start Condition ...................................... 129

Brown-out Reset....................................................... 225

Bus Collision During a Repeated

Start Condition (Case 1) ................................... 130

Bus Collision During a Repeated

Start Condition (Case 2) ................................... 130

Bus Collision During a Stop Condition

(Case 1)............................................................ 131

Bus Collision During a Stop Condition

(Case 2)............................................................ 131

Bus Collision During Start Condition

(SCL = 0) .......................................................... 129

Bus Collision During Start Condition

(SDA Only) ....................................................... 128

Bus Collision for Transmit and

Acknowledge .................................................... 127

Capture/Compare/PWM

(CCP1 and CCP2) ............................................ 227

CLKO and I/O ........................................................... 224

Clock Synchronization .............................................. 113

External Clock .......................................................... 223

Fail-Safe Clock Monitor ............................................ 189

First Start Bit ............................................................. 121

I

2

C Bus Data............................................................. 232

I

2

C Bus Start/Stop Bits ............................................. 231

I

2

C Master Mode (Reception,

7-bit Address) ................................................... 125

2

I C Master Mode (Transmission,

7 or 10-bit Address) .......................................... 124

2

I C Slave Mode (Transmission,

10-bit Address) ................................................. 111

2

C Slave Mode (Transmission,

I

7-bit Address) ................................................... 109

2

I C Slave Mode with SEN = 0 (Reception,

10-bit Address) ................................................. 110

2

I C Slave Mode with SEN = 0 (Reception,

7-bit Address) ................................................... 108

2

I C Slave Mode with SEN = 1 (Reception,

10-bit Address) ................................................. 115

I

2

C Slave Mode with SEN = 1 (Reception,

7-bit Address) ................................................... 114

Low-Voltage Detect .................................................. 177

LP Clock to Primary System Clock after

Reset (EC, RC, INTRC)...................................... 46

LP Clock to Primary System Clock after

Reset (HS, XT, LP)............................................. 45

Parallel Slave Port .................................................... 228

Parallel Slave Port Read ............................................ 71

T

T1CKPS0 Bit ....................................................................... 78

T1CKPS1 Bit ....................................................................... 78

T1OSCEN Bit ...................................................................... 78

T1SYNC Bit......................................................................... 78

T2CKPS0 Bit ....................................................................... 86

T2CKPS1 Bit ....................................................................... 86

T

AD

.................................................................................... 157

Timer0 ................................................................................. 73

Associated Registers .................................................. 76

Clock Source Edge Select (T0SE Bit)......................... 22

Clock Source Select (T0CS Bit).................................. 22

Interrupt....................................................................... 73

Operation .................................................................... 73

Overflow Enable (TMR0IE Bit).................................... 23

Overflow Flag (TMR0IF Bit) ...................................... 185

Overflow Interrupt ..................................................... 185

Prescaler..................................................................... 74

T0CKI.......................................................................... 74

Use with External Clock .............................................. 74

Timer1 ................................................................................. 77

Associated Registers .................................................. 83

Asynchronous Counter Mode ..................................... 80

Reading and Writing ........................................... 80

Capacitor Selection..................................................... 81

Counter Operation ...................................................... 79

Operation .................................................................... 77

Operation in Synchronized

Counter Mode ..................................................... 79

Operation in Timer Mode ............................................ 79

Oscillator ..................................................................... 81

Oscillator Layout Considerations ................................ 81

Prescaler..................................................................... 82

Resetting Timer1 Register Pair................................... 82

Resetting Using a CCP Trigger Output....................... 81

Use as a Real-Time Clock .......................................... 82

Timer2 ................................................................................. 85

Associated Registers .................................................. 86

Output ......................................................................... 85

Postscaler ................................................................... 85

Prescaler..................................................................... 85

Prescaler and Postscaler ............................................ 85



2004 Microchip Technology Inc.

DS30498C-page 269

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