PIC16F767-I/SP 参数 Datasheet PDF下载

PIC16F7X7

FIGURE 18-18:

RC6/TX/CK

pin

RC7/RX/DT

pin

120

122

Note:

Refer to Figure 18-4 for load conditions.

AUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

121

121

TABLE 18-13: AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param

No.

120

Symbol

Characteristic

Min

Typ†

Max

Units Conditions

T

CK

H2

DT

V SYNC XMIT (MASTER & SLAVE)

Clock High to Data Out Valid

T

CKRF

T

DTRF

Clock Out Rise Time and Fall Time

(Master mode)

Data Out Rise Time and Fall Time

PIC16F7X7

PIC16LF7X7

PIC16F7X7

PIC16LF7X7

PIC16F7X7

PIC16LF7X7

—

—

—

—

—

—

—

—

—

—

—

—

80

100

45

50

45

50

ns

ns

ns

ns

ns

ns

121

122

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

FIGURE 18-19:

RC6/TX/CK

pin

RC7/RX/DT

pin

AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

125

126

Note:

Refer to Figure 18-4 for load conditions.

TABLE 18-14: AUSART SYNCHRONOUS RECEIVE REQUIREMENTS

Param

No.

125

126

Symbol

T

DT

V2

CK

L

T

CK

L2

DTL

Characteristic

SYNC RCV (MASTER & SLAVE)

Data Setup before CK

↓

(DT setup time)

Data Hold after CK

↓

(DT hold time)

Min

Typ†

Max

Units

Conditions

15

15

—

—

—

—

ns

ns

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS30498C-page 234



2004 Microchip Technology Inc.