PIC16F7X7
FIGURE 18-11:
PARALLEL SLAVE PORT TIMING (PIC16F747/777 DEVICES ONLY)
RE2/CS/AN7
RE0/RD/AN5
RE1/WR/AN6
65
RD7/PSP7:RD0/PSP0
62
64
63
Note: Refer to Figure 18-4 for load conditions.
TABLE 18-9: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F747/777 DEVICES ONLY)
Param
No.
Symbol
Characteristic
Min Typ† Max Units
Conditions
62
TDTV2WRH Data In Valid before WR ↑ or CS ↑ (setup time)
20
25
—
—
—
—
ns
ns
Extended range only
63*
TWRH2DTI WR ↑ or CS ↑ to Data In Invalid
PIC16F7X7
20
35
—
—
—
—
ns
ns
(hold time)
PIC16LF7X7
64
65
TRDL2DTV RD ↓ and CS ↓ to Data Out Valid
—
—
—
—
80
90
ns
ns
Extended range only
TRDH2DTI
RD ↑ or CS ↓ to Data Out Invalid
10
—
30
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS30498C-page 228
2004 Microchip Technology Inc.