PIC16F7X7
FIGURE 18-20:
A/D CONVERSION TIMING
1 T
CY
(T
OSC
/2)
(1)
Q4
130
A/D CLK
A/D DATA
ADRES
ADIF
GO
Sampling Stopped
DONE
132
9
8
7
...
...
2
1
0
NEW_DATA
131
BSF ADCON0, GO
OLD_DATA
SAMPLE
Note:
If the A/D clock source is selected as RC, a time of T
CY
is added before the A/D clock starts. This allows the
SLEEP
instruction to be executed.
TABLE 18-16: A/D CONVERSION REQUIREMENTS
Param
Symbol
No.
130
T
AD
Characteristic
A/D Clock Period
PIC16F7X7
PIC16LF7X7
PIC16F7X7
PIC16LF7X7
131
132
T
CNV
T
ACQ
Conversion Time (not including S/H time)
(Note 1)
Acquisition Time
(Note 2)
10*
Min
1.6
3.0
2.0
3.0
Typ†
—
—
4.0
6.0
—
40
—
Max
—
—
6.0
9.0
12
—
—
Units
µs
µs
µs
µs
T
AD
µs
µs
The minimum time is the
amplifier settling time. This may
be used if the “new” input
voltage has not changed by
more than 1 LSb (i.e., 5.0 mV @
5.12V) from the last sampled
voltage (as stated on C
HOLD
).
If the A/D clock source is
selected as RC, a time of T
CY
is
added before the A/D clock
starts. This allows the
SLEEP
instruction to be executed.
Conditions
T
OSC
based, V
REF
≥
3.0V
T
OSC
based, V
REF
≥
2.0V
A/D RC mode
A/D RC mode
134
T
GO
Q4 to A/D Clock Start
—
T
OSC
/2 §
—
—
*
†
§
Note 1:
2:
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
This specification ensured by design.
ADRES register may be read on the following T
CY
cycle.
See
for minimum conditions.
DS30498C-page 236
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
