PIC16F7X7
EXAMPLE 6-1:
CLRWDT
BANKSEL
MOVLW
MOVWF
CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0
;
;
;
;
Clear WDT and prescaler
Select Bank of OPTION_REG
Select TMR0, new prescale
value and clock source
OPTION_REG
b'xxxx0xxx'
OPTION_REG
TABLE 6-1:
Address
01h,101h
0Bh,8Bh,
10Bh,18Bh
81h,181h
Legend:
REGISTERS ASSOCIATED WITH TIMER0
Name
TMR0
INTCON
OPTION_REG
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
xxxx xxxx
Value on
all other
Resets
uuuu uuuu
0000 000u
1111 1111
Timer0 Module Register
GIE
RBPU
PEIE
INTEDG
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
0000 000x
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
x
= unknown,
u
= unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
DS30498C-page 76
2004 Microchip Technology Inc.