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PIC16F767-I/SP 参数 Datasheet PDF下载

PIC16F767-I/SP图片预览
型号: PIC16F767-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚, 8位CMOS闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin, 8-Bit CMOS Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 276 页 / 4898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F7X7  
15.15.1 INT INTERRUPT  
15.15.3 PORTB INTCON CHANGE  
External interrupt on the RB0/INT pin is edge-triggered,  
either rising if bit INTEDG (OPTION_REG<6>) is set or  
falling if the INTEDG bit is clear. When a valid edge  
appears on the RB0/INT pin, flag bit INT0IF  
(INTCON<1>) is set. This interrupt can be disabled by  
clearing enable bit, INT0IE (INTCON<4>). Flag bit  
INT0IF must be cleared in software in the Interrupt  
Service Routine before re-enabling this interrupt. The  
INT interrupt can wake-up the processor from Sleep if  
bit INT0IE was set prior to going into Sleep. The status  
of Global Interrupt Enable bit, GIE, decides whether or  
not the processor branches to the interrupt vector  
following wake-up. See Section 15.18 “Power-Down  
Mode (Sleep)” for details on Sleep mode.  
An input change on PORTB<7:4> sets flag bit, RBIF  
(INTCON<0>). The interrupt can be enabled/disabled  
by setting/clearing enable bit, RBIE (INTCON<4>), see  
Section 2.2 “Data Memory Organization”.  
15.16 Context Saving During Interrupts  
During an interrupt, only the return PC value is saved  
on the stack. Typically, users may wish to save key  
registers during an interrupt (i.e., W, Status registers).  
Since the upper 16 bytes of each bank are common in  
the PIC16F7X7 devices, temporary holding registers,  
W_TEMP, STATUS_TEMP and PCLATH_TEMP,  
should be placed in here. These 16 locations don’t  
require banking and therefore, make it easier for  
context save and restore. The same code shown in  
Example 15-1 can be used.  
15.15.2 TMR0 INTERRUPT  
An overflow (FFh 00h) in the TMR0 register will set  
flag bit, TMR0IF (INTCON<2>). The interrupt can be  
enabled/disabled by setting/clearing enable bit,  
TMR0IE (INTCON<5>), see Section 6.0 “Timer0  
Module”.  
EXAMPLE 15-1:  
SAVING STATUS AND W REGISTERS IN RAM  
MOVWF  
SWAPF  
CLRF  
MOVWF  
:
W_TEMP  
STATUS, W  
STATUS  
;Copy W to TEMP register  
;Swap status to be saved into W  
;bank 0, regardless of current bank, Clears IRP,RP1,RP0  
;Save status to bank zero STATUS_TEMP register  
STATUS_TEMP  
:(ISR)  
:
;Insert user code here  
SWAPF  
STATUS_TEMP, W  
;Swap STATUS_TEMP register into W  
;(sets bank to original state)  
;Move W into STATUS register  
;Swap W_TEMP  
MOVWF  
SWAPF  
SWAPF  
STATUS  
W_TEMP, F  
W_TEMP, W  
;Swap W_TEMP into W  
2004 Microchip Technology Inc.  
DS30498C-page 185  
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