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    S1220PBIC 参数 Datasheet PDF下载

    S1220PBIC图片预览
    型号： S1220PBIC
    PDF下载： 下载PDF文件 查看货源
    内容描述： [Clock Recovery Circuit, 1-Func, CMOS, PBGA196, PLASTIC, BGA-196]
    分类和应用： ATM异步传输模式电信电信集成电路
    文件页数/大小： 43 页 / 1040 K
    品牌： AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
     浏览型号S1220PBIC的Datasheet PDF文件第1页浏览型号S1220PBIC的Datasheet PDF文件第2页浏览型号S1220PBIC的Datasheet PDF文件第4页浏览型号S1220PBIC的Datasheet PDF文件第5页浏览型号S1220PBIC的Datasheet PDF文件第6页浏览型号S1220PBIC的Datasheet PDF文件第7页浏览型号S1220PBIC的Datasheet PDF文件第8页浏览型号S1220PBIC的Datasheet PDF文件第9页  
    S1220 – SONET/SDH/ATM Quad OC-3/12
    with Clock Data Recovery (CDR)
    LIST OF FIGURES
    Revision 3.03 – May 25, 2007
    Advance Data Sheet
    Figure 1. System Block Diagram ............................................................................................................................. 1
    Figure 2. Functional Block Diagram, Non-MII Mode ................................................................................................ 6
    Figure 3. Functional Block Diagram, MII Mode ........................................................................................................ 7
    Figure 4. SONET Structure ...................................................................................................................................... 8
    Figure 5. Input Jitter Tolerance .............................................................................................................................. 13
    Figure 6. Jitter Transfer Specification .................................................................................................................... 13
    Figure 7. S1220 Pinout Top View (for Non-MII Mode only) ................................................................................... 23
    Figure 8. S1220 Pinout Top View (for MII Mode only) ........................................................................................... 24
    Figure 9. S1220 – 196 PBGA Package Mechanical Drawing ................................................................................ 25
    Figure 10. S1220 – 196 PBGA Package Marking Drawing (Top View) ................................................................. 26
    Figure 11. S1220 - 19.44 MHz, 77.76 MHz, and 155.52 MHz REFCLK Phase Noise Limit .................................. 28
    Figure 12. Serial Interface Timing .......................................................................................................................... 35
    Figure 13. RESET Requirement ............................................................................................................................ 36
    Figure 14. Differential Voltage Measurement ........................................................................................................ 37
    Figure 15. LVCMOS Input/Output Buffers ............................................................................................................. 37
    Figure 16. S1220 Differential LVDS/LVPECL Output Buffers ................................................................................ 37
    Figure 17. Differential LVPECL Output to Differential LVPECL Input DC Coupled Termination ............................ 38
    Figure 18. Differential LVPECL Output to Differential LVPECL Input AC Coupled Termination VDDH = 3.3 V .... 38
    Figure 19. Differential LVDS Input DC Coupled Termination, VDDH=2.5 V or 3.3 V ............................................ 39
    Figure 20. Differential LVDS Input AC Coupled Termination, VDDH=2.5 V or 3.3 V ............................................. 39
    Figure 21. Differential LVDS Driver to LVDS Input Termination ............................................................................ 39
    Figure 22. Differential LVDS Output to LVDS Input AC Coupled Termination ....................................................... 40
    Figure 23. Differential LVPECL Output to Differential LVPECL Input AC Coupled Termination (Internal Biased) 40
    Figure 24. Differential LVPECL Output to Differential LVPECL Input AC Coupled Termination (Not internal Biased) .40
    Figure 25. 3.3 V Differential LVPECL Oscillator to Reference Clock Input AC Coupled Termination .................... 41
    Figure 26. 3.3 V Differential LVPECL Oscillator to Reference Clock Input DC Coupled Termination ................... 41
    Figure 27. Differential LVDS Output to Differential LVDS Input AC Coupled Termination ..................................... 41
    AMCC Confidential and Proprietary
    DS2018
    3

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