S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Figure 2. Functional Block Diagram, Non-MII Mode
PLL CLOCK
Synthesizer
Revision 3.03 – May 25, 2007
Advance Data Sheet
TSCLKP/N
REFCLK
SD0
RATESEL0
REFCKINP
REFCKINN
REFCLK
LOCKDET0
SERDATIP0
SERDATIN0
PLL CLOCK
RECOVERY
BITCLK
D
Q
QN
SERDATOP0
SERDATON0
REFSEL1
REFSEL0
SD1
RATESEL1
0 0
0 1
1 X
19.44 MHz
77.76 MHz
155.52 MHz
SERDATIP1
SERDATIN1
PLL CLOCK
RECOVERY
BITCLK
Q
D QN
SERDATOP1
SERDATON1
REFCLK
SERCLKOP0
SERCLKON0
Div
155CK0
LOCKDET1
MODE 1
MODE 0
SD2
MII Mode
RATESEL2
1 1
1 0
0 1
NON-MII Mode
Factory TEST
Mode
Internal Mode
REFCLK
PLL CLOCK
RECOVERY
LOCKDET2
SERCLKOP1
SERCLKON1
0 0
Div
155CK1
SERDATIP2
SERDATIN2
BITCLK
Q
D QN
SERDATOP2
SERDATON2
SD3
RATESEL3
REFCLK
SERCLKOP2
SERCLKON2
Div
155CK2
LOCKDET3
SERDATIP3
SERDATIN3
COREOFFB
COREOFFA
A
0
0
1
1
B
0
1
0
1
PLL CLOCK
RECOVERY
BITCLK
D
Q
QN
SERDATOP3
SERDATON3
SDPOL
RSTB
SERCLKOOFF
TSCLKOOFF
CLVDSPECLB
DCBIAS
XLVDSPECLB
RX155EN
All 4 channels
All Cores on
Cores 0,1,2 on, Core 3 off
Cores 0,1 on, Cores 2, 3 off
Core 0 on, Cores 1,2,3 off
SERCLKOP3
SERCLKON3
Div
155CK3
6
DS2018
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
