Revision 3.03 – May 25, 2007
S1220 – SONET/SDH/ATM Quad OC-3/12
with Clock Data Recovery (CDR)
Advance Data Sheet
Table 14. Performance Specifications (Continued)
Parameter
Min
Typ
Max
Units
Conditions
Frequency difference at which receive PLL goes into
lock (REFCLK compared to the divided down VCO
clock).
244
366
ppm
Previously out of lock.
Valid for OC-3/OC-12.
Guaranteed by design but
not tested.
OC-3/STS-3/OC-12/STS-12
Jitter Tolerance
0.4
UI
Sinusoidal input jitter. Ampli-
tude on RSDP/N data inputs
from:
250 kHz to 5 MHz (OC-12)
250 kHz to 1.3 MHz (OC-3)
Reference Clock Requirements
Reference Clock
Frequency Tolerance
-100
40
+100
ppm
Required ± 20 ppm for
TSCLK to meet SONET out-
put frequency specification.
Reference Clock
Input Duty Cycle
60
% of
UI
Reference Clock Rise & Fall Times
2.0
ns
20% to 80% of amplitude.
Figure 11. S1220 - 19.44 MHz, 77.76 MHz, and 155.52 MHz REFCLK Phase Noise Limit
-50
-70
-90
155.52 MHz
77.76 MHz
19.44 MHz
-110
-130
-150
-170
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Freq (Hz)
Note: The chart above shows the phase noise limit for a selected Reference Clock (REFCLK) input, specific for TSCLK or for Serial Clock Out-
put (SERCLKO) when locked to reference. In order to meet the SONET spec, the individual REFCLK spec needs to be below the indi-
cated curves.
28
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